[all-commits] [llvm/llvm-project] abc1ac: [TargetLowering][AMDGPU][ARM][RISCV][X86] Teach Si...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: abc1acf8df3b212a03650c314b7832b3aa7ccd42
      https://github.com/llvm/llvm-project/commit/abc1acf8df3b212a03650c314b7832b3aa7ccd42
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-08-14 (Wed, 14 Aug 2024)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/test/CodeGen/AArch64/srem-seteq-illegal-types.ll
    M llvm/test/CodeGen/AMDGPU/permute_i8.ll
    M llvm/test/CodeGen/AMDGPU/srem-seteq-illegal-types.ll
    M llvm/test/CodeGen/ARM/srem-seteq-illegal-types.ll
    M llvm/test/CodeGen/Mips/srem-seteq-illegal-types.ll
    M llvm/test/CodeGen/PowerPC/srem-seteq-illegal-types.ll
    M llvm/test/CodeGen/RISCV/div.ll
    M llvm/test/CodeGen/RISCV/rv64zba.ll
    M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
    M llvm/test/CodeGen/Thumb2/srem-seteq-illegal-types.ll
    M llvm/test/CodeGen/X86/srem-seteq-illegal-types.ll

  Log Message:
  -----------
  [TargetLowering][AMDGPU][ARM][RISCV][X86] Teach SimplifyDemandedBits to combine (srl (sra X, C1), ShAmt) -> sra(X, C1+ShAmt) (#101751)

If the upper bits of the shr aren't demanded.

This helps with cases where the outer srl was originally an sra and was
converted to a srl by SimplifyDemandedBits before it had a chance to
combine with the inner sra. This can occur when the inner sra was part
of a sign_extend_inreg expansion.

There are some regressions in ARM and Thumb2.



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