[all-commits] [llvm/llvm-project] 5ab99b: [RISCV] Add scheduling model for Syntacore SCR4 an...

[Anton Sidorenko via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5ab99bf1a757c5ad7115280f374d9af4f1b98bc9
      https://github.com/llvm/llvm-project/commit/5ab99bf1a757c5ad7115280f374d9af4f1b98bc9
  Author: Anton Sidorenko <anton.sidorenko at syntacore.com>
  Date:   2024-08-14 (Wed, 14 Aug 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCV.td
    M llvm/lib/Target/RISCV/RISCVProcessors.td
    R llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR3.td
    A llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR345.td
    R llvm/test/tools/llvm-mca/RISCV/SyntacoreSCR/SCR3-ALU.s
    R llvm/test/tools/llvm-mca/RISCV/SyntacoreSCR/SCR3-LSU.s
    A llvm/test/tools/llvm-mca/RISCV/SyntacoreSCR/SCR3_4_5-ALU.s
    A llvm/test/tools/llvm-mca/RISCV/SyntacoreSCR/SCR3_4_5-LSU.s
    A llvm/test/tools/llvm-mca/RISCV/SyntacoreSCR/SCR4_5-FPU.s

  Log Message:
  -----------
  [RISCV] Add scheduling model for Syntacore SCR4 and SCR5  (#102909)

Syntacore SCR4 is a microcontroller-class processor core that has much
in common with SCR3, but also supports F and D extensions.
Overview: https://syntacore.com/products/scr4

Syntacore SCR5 is an entry-level Linux-capable 32/64-bit RISC-V
processor core which scheduling model almost match SCR4.
Overview: https://syntacore.com/products/scr5

Co-authored-by: Dmitrii Petrov <dmitrii.petrov at syntacore.com>
Co-authored-by: Anton Afanasyev <anton.afanasyev at syntacore.com>



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications