[all-commits] [llvm/llvm-project] afd42f: [AMDGPU][True16][CodeGen] Support AND/OR/XOR and L...

[Brox Chen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: afd42fb3038904e8c09c0fb735e713bc052ec0e4
      https://github.com/llvm/llvm-project/commit/afd42fb3038904e8c09c0fb735e713bc052ec0e4
  Author: Brox Chen <broxigarchen at outlook.com>
  Date:   2024-08-13 (Tue, 13 Aug 2024)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
    M llvm/lib/Target/AMDGPU/SIInstructions.td
    M llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
    M llvm/lib/Target/AMDGPU/VOP1Instructions.td
    M llvm/lib/Target/AMDGPU/VOP2Instructions.td
    M llvm/lib/Target/AMDGPU/VOP3Instructions.td
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s16.mir
    M llvm/test/CodeGen/AMDGPU/bf16.ll
    M llvm/test/CodeGen/AMDGPU/fadd.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.floor.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll
    M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2.txt

  Log Message:
  -----------
  [AMDGPU][True16][CodeGen] Support AND/OR/XOR and LDEXP True16 format (#102620)

Support AND/OR/XOR true16 and LDEXP true/fake16 format.

These instructions are previously implemented with fake16 profile.
Fixing the implementation.

Added a RA hint so that when using 16bit register in a 32bit
instruction, try to use the register directly without an extra 16bit
move

---------

Co-authored-by: guochen2 <guochen2 at amd.com>



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