[all-commits] [llvm/llvm-project] ed7ad0: [X86] Promote cttz_i32(x) -> cttz_i64((i64)x | (1 ...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ed7ad0a1a0584f90a211ca5a87bc46968e169e5d
      https://github.com/llvm/llvm-project/commit/ed7ad0a1a0584f90a211ca5a87bc46968e169e5d
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2024-08-13 (Tue, 13 Aug 2024)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/Analysis/CostModel/X86/cttz-codesize.ll
    M llvm/test/Analysis/CostModel/X86/cttz-latency.ll
    M llvm/test/Analysis/CostModel/X86/cttz-sizelatency.ll
    M llvm/test/Analysis/CostModel/X86/intrinsic-cost-kinds.ll
    M llvm/test/CodeGen/X86/cttz.ll
    M llvm/test/CodeGen/X86/known-never-zero.ll
    M llvm/test/CodeGen/X86/pr89877.ll
    M llvm/test/CodeGen/X86/pr90847.ll

  Log Message:
  -----------
  [X86] Promote cttz_i32(x) -> cttz_i64((i64)x | (1 << 32)) (#102900) (REAPPLIED)

On 64bit targets we can promote i32 CTTZ nodes to i64 CTTZ_ZERO_UNDEF by setting the 32nd bit.

#57811 also queried about whether we should use BTS instead of MOVABS+OR to avoid a i64 immediate - I'm willing to tweak the DAGToDAG isel peephole for these cases if reviewers think it worthwhile. But most recent CPUs can actually handle MOVABS faster than BTS/C/R.......

Reapplied with missing costmodel changes - the cost tables can probably be improved in a follow up patch.

Fixes #57811



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