[all-commits] [llvm/llvm-project] f9c980: [SPIR-V] Rework usage of virtual registers' types ...

[Vyacheslav Levytskyy via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f9c98068c852c1bb1ec029c2c8df8ace9605f16f
      https://github.com/llvm/llvm-project/commit/f9c98068c852c1bb1ec029c2c8df8ace9605f16f
  Author: Vyacheslav Levytskyy <vyacheslav.levytskyy at intel.com>
  Date:   2024-08-12 (Mon, 12 Aug 2024)

  Changed paths:
    M llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp
    M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
    M llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
    M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
    M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
    M llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
    M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
    M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
    M llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
    M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
    M llvm/lib/Target/SPIRV/SPIRVRegisterBanks.td
    M llvm/lib/Target/SPIRV/SPIRVRegisterInfo.td
    M llvm/test/CodeGen/SPIRV/SampledImageRetType.ll
    M llvm/test/CodeGen/SPIRV/atomicrmw.ll
    M llvm/test/CodeGen/SPIRV/basic_int_types.ll
    M llvm/test/CodeGen/SPIRV/empty.ll
    M llvm/test/CodeGen/SPIRV/event-zero-const.ll
    M llvm/test/CodeGen/SPIRV/expect.ll
    M llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_add/atomicrmw_faddfsub_double.ll
    M llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_add/atomicrmw_faddfsub_float.ll
    M llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_add/atomicrmw_faddfsub_half.ll
    M llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_min_max/atomicrmw_fminfmax_double.ll
    M llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_min_max/atomicrmw_fminfmax_float.ll
    M llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_min_max/atomicrmw_fminfmax_half.ll
    M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_cache_controls/basic-load-store.ll
    M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_usm_storage_classes/intel-usm-addrspaces.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/all.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/any.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/imad.ll
    M llvm/test/CodeGen/SPIRV/instructions/atomic.ll
    M llvm/test/CodeGen/SPIRV/instructions/integer-casts.ll
    M llvm/test/CodeGen/SPIRV/instructions/ptrcmp.ll
    M llvm/test/CodeGen/SPIRV/linkage/link-attribute.ll
    M llvm/test/CodeGen/SPIRV/literals.ll
    M llvm/test/CodeGen/SPIRV/lshr-constexpr.ll
    M llvm/test/CodeGen/SPIRV/opencl/image.ll
    M llvm/test/CodeGen/SPIRV/pointers/irtrans-added-int-const-32-64.ll
    M llvm/test/CodeGen/SPIRV/pointers/type-deduce-global-dup.ll
    M llvm/test/CodeGen/SPIRV/transcoding/OpImageSampleExplicitLod.ll
    M llvm/test/CodeGen/SPIRV/transcoding/OpImageWrite.ll
    M llvm/test/CodeGen/SPIRV/transcoding/OpVectorInsertDynamic_i16.ll
    M llvm/test/CodeGen/SPIRV/transcoding/SampledImage.ll
    M llvm/test/CodeGen/SPIRV/transcoding/cl-types.ll
    M llvm/test/CodeGen/SPIRV/transcoding/fadd.ll
    M llvm/test/CodeGen/SPIRV/transcoding/group_ops.ll
    M llvm/test/CodeGen/SPIRV/transcoding/image_with_access_qualifiers.ll
    M llvm/test/CodeGen/SPIRV/transcoding/non32.ll
    M llvm/test/CodeGen/SPIRV/transcoding/spirv-private-array-initialization.ll
    M llvm/test/CodeGen/SPIRV/transcoding/spirv-types.ll
    M llvm/test/CodeGen/SPIRV/transcoding/sub_group_extended_types.ll
    M llvm/test/CodeGen/SPIRV/transcoding/sub_group_shuffle.ll
    M llvm/test/CodeGen/SPIRV/transcoding/sub_group_shuffle_relative.ll
    M llvm/test/CodeGen/SPIRV/types/or-i1.ll
    M llvm/test/CodeGen/SPIRV/unnamed-global.ll
    M llvm/test/CodeGen/SPIRV/var-uniform-const.ll

  Log Message:
  -----------
  [SPIR-V] Rework usage of virtual registers' types and classes (#101732)

This PR contains changes in virtual register processing aimed to improve
correctness of emitted MIR between passes from the perspective of
MachineVerifier. This potentially helps to detect previously missed
flaws in code emission and harden the test suite. As a measure of
correctness and usefulness of this PR we may use a mode with expensive
checks set on, and MachineVerifier reports problems in the test suite.

In order to satisfy Machine Verifier requirements to MIR correctness not
only a rework of usage of virtual registers' types and classes is
required, but also corrections into pre-legalizer and instruction
selection logics. Namely, the following changes are introduced:
* scalar virtual registers have proper bit width,
* detect register class by SPIR-V type,
* add a superclass for id virtual register classes,
* fix Tablegen rules used for instruction selection,
* fixes of minor existed issues (missed flag for proper representation
of a null constant for OpenCL vs. HLSL, wrong usage of integer virtual
registers as a synonym of any non-type virtual register).



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