[all-commits] [llvm/llvm-project] f0df4f: [LV] Support generating masks for switch terminato...

[Florian Hahn via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f0df4fbd0c7b6bb369ceaa1fd6f9e0c88d781ae5
      https://github.com/llvm/llvm-project/commit/f0df4fbd0c7b6bb369ceaa1fd6f9e0c88d781ae5
  Author: Florian Hahn <flo at fhahn.com>
  Date:   2024-08-11 (Sun, 11 Aug 2024)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
    M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
    M llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
    M llvm/test/Transforms/LoopVectorize/X86/predicate-switch.ll
    M llvm/test/Transforms/LoopVectorize/no_switch.ll
    M llvm/test/Transforms/LoopVectorize/predicate-switch.ll
    M llvm/test/Transforms/LoopVectorize/vplan-predicate-switch.ll
    M llvm/test/Transforms/PhaseOrdering/X86/pr48844-br-to-switch-vectorization.ll

  Log Message:
  -----------
  [LV] Support generating masks for switch terminators. (#99808)

Update createEdgeMask to created masks where the terminator in Src is a
switch. We need to handle 2 separate cases:

1. Dst is not the default desintation. Dst is reached if any of the
cases with destination == Dst are taken. Join the conditions for each
case where destination == Dst using a logical OR.
2. Dst is the default destination. Dst is reached if none of the cases
with destination != Dst are taken. Join the conditions for each case
where the destination is != Dst using a logical OR and negate it.

Edge masks are created for every destination of cases and/or 
default when requesting a mask where the source is a switch.

Fixes https://github.com/llvm/llvm-project/issues/48188.

PR: https://github.com/llvm/llvm-project/pull/99808



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