[all-commits] [llvm/llvm-project] c25c15: [AArch64] Don't replace dst of SWP instructions wi...

[Lucas Duarte Prates via All-commits]

  Branch: refs/heads/release/19.x
  Home:   https://github.com/llvm/llvm-project
  Commit: c25c15edb1cc58796ede2071d4fdbdd1575bcd66
      https://github.com/llvm/llvm-project/commit/c25c15edb1cc58796ede2071d4fdbdd1575bcd66
  Author: Lucas Duarte Prates <lucas.prates at arm.com>
  Date:   2024-08-10 (Sat, 10 Aug 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
    A llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-exchange-fence.ll

  Log Message:
  -----------
  [AArch64] Don't replace dst of SWP instructions with (X|W)ZR (#102139)

This change updates the AArch64DeadRegisterDefinition pass to ensure it
does not replace the destination register of a SWP instruction with the
zero register when its value is unused. This is necessary to ensure that
the ordering of such instructions in relation to DMB.LD barries adheres
to the definitions of the AArch64 Memory Model.

The memory model states the following (ARMARM version DDI 0487K.a
§B2.3.7):
```
Barrier-ordered-before

An effect E1 is Barrier-ordered-before an effect E2 if one of the following applies:
[...]
* All of the following apply:
- E1 is a Memory Read effect.
- E1 is generated by an instruction whose destination register is not WZR or XZR.
- E1 appears in program order before E3.
- E3 is either a DMB LD effect or a DSB LD effect.
- E3 appears in program order before E2.
```

Prior to this change, by replacing the destination register of such SWP
instruction with WZR/XZR, the ordering relation described above was
incorrectly removed from the generated code.

The new behaviour is ensured in this patch by adding the relevant
`SWP[L](B|H|W|X)` instructions to list in the `atomicReadDroppedOnZero`
predicate, which already covered the `LD<Op>` instructions that are
subject to the same effect.

Fixes #68428.

(cherry picked from commit beb37e2e22b549b361be7269a52a3715649e956a)



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