[all-commits] [llvm/llvm-project] 02645d: [RISCV] Add Syntacore SCR5 RV32/64 processors defi...

[Anton Sidorenko via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 02645d66f93809f7f52b742987f350793136221f
      https://github.com/llvm/llvm-project/commit/02645d66f93809f7f52b742987f350793136221f
  Author: Anton Sidorenko <anton.sidorenko at syntacore.com>
  Date:   2024-08-09 (Fri, 09 Aug 2024)

  Changed paths:
    M clang/test/Driver/riscv-cpus.c
    M clang/test/Misc/target-invalid-cpu-note.c
    M llvm/docs/ReleaseNotes.rst
    M llvm/lib/Target/RISCV/RISCVProcessors.td

  Log Message:
  -----------
  [RISCV] Add Syntacore SCR5 RV32/64 processors definition (#102285)

Syntacore SCR5 is an entry-level Linux-capable 32/64-bit RISC-V
processor core.
Overview: https://syntacore.com/products/scr5

Scheduling model will be added in a subsequent PR.

Co-authored-by: Dmitrii Petrov <dmitrii.petrov at syntacore.com>
Co-authored-by: Anton Afanasyev <anton.afanasyev at syntacore.com>



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