[all-commits] [llvm/llvm-project] ac3f1d: [Clang][Sema] Make UnresolvedLookupExprs in class ...
Akash Banerjee via All-commits
all-commits at lists.llvm.org
Thu Aug 8 10:17:05 PDT 2024
Branch: refs/heads/users/akash/set-composite
Home: https://github.com/llvm/llvm-project
Commit: ac3f1d7d7869688d4f6cf6b59557d76c35be55a7
https://github.com/llvm/llvm-project/commit/ac3f1d7d7869688d4f6cf6b59557d76c35be55a7
Author: Krystian Stasiowski <sdkrystian at gmail.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M clang/include/clang/AST/ExprCXX.h
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ExprCXX.cpp
M clang/lib/Sema/SemaCoroutine.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaExprMember.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/TreeTransform.h
M clang/test/SemaCXX/decltype.cpp
Log Message:
-----------
[Clang][Sema] Make UnresolvedLookupExprs in class scope explicit specializations instantiation dependent (#100392)
A class member named by an expression in a member function that may instantiate to a static _or_ non-static member is represented by a `UnresolvedLookupExpr` in order to defer the implicit transformation to a class member access expression until instantiation. Since `ASTContext::getDecltypeType` only creates a `DecltypeType` that has a `DependentDecltypeType` as its canonical type when the operand is instantiation dependent, and since we do not transform types unless they are instantiation dependent, we need to mark the `UnresolvedLookupExpr` as instantiation dependent in order to correctly build a `DecltypeType` using the expression as its operand with a `DependentDecltypeType` canonical type. Fixes #99873.
Commit: 6a576de508fcfa8c499a511e53fd78a16fca86e1
https://github.com/llvm/llvm-project/commit/6a576de508fcfa8c499a511e53fd78a16fca86e1
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M clang/lib/Parse/ParseOpenMP.cpp
M clang/lib/Serialization/ASTReader.cpp
Log Message:
-----------
[NFC] Fix compile warning introduced in #99732
Commit: 9f9cd3d794a364d6482afdf583b2182e2a4fd784
https://github.com/llvm/llvm-project/commit/9f9cd3d794a364d6482afdf583b2182e2a4fd784
Author: Yeoul Na <yeoul_na at apple.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M clang/include/clang/Sema/Sema.h
M clang/lib/Sema/SemaBoundsSafety.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
Log Message:
-----------
[BoundsSafety][NFC] Remove the unused parameter 'Decls' from 'Sema::C… (#102076)
…heckCountedByAttrOnField'
llvm::SmallVectorImpl<TypeCoupledDeclRefInfo> &Decls is a vector of
declarations referred to by the argument of 'counted_by' attributes and
fields. 'BuildCountAttributedArrayOrPointerType' had been made
self-contained to produce the 'Decls' within itself to allow
'TreeTransform' to invoke the function without having to call
'Sema::CheckCountedByAttrOnField' again. Thus, 'Decls' produced by
`Sema::CheckCountedByAttrOnField` is never used.
Commit: 591557ccba90ab3faae4dc13d1dfeed21c536fe5
https://github.com/llvm/llvm-project/commit/591557ccba90ab3faae4dc13d1dfeed21c536fe5
Author: Steven Wu <stevenwu at apple.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M clang/test/Modules/crash-vfs-include-pch.m
Log Message:
-----------
[Test] Update clang/test/Modules/crash-vfs-include-pch.m (#102080)
Avoid the driver error for mis-using a clang cc1 flag as driver flag in
the crash test.
Commit: 9ca6fdd8cadb1f86a05c9bf460e660d8d07591b4
https://github.com/llvm/llvm-project/commit/9ca6fdd8cadb1f86a05c9bf460e660d8d07591b4
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/always_uniform.ll
Log Message:
-----------
AMDGPU: Add some leaf intrinsics to isAlwaysUniform (#101925)
These would always be uniform anyway, but it shouldn't hurt to
mark them as always uniform. This will help use TTI::isAlwaysUniform
in place of proper uniformity analysis in trivial situations.
Commit: 23171e56e43b70a8a4d768cc4b5915a19f9a3b87
https://github.com/llvm/llvm-project/commit/23171e56e43b70a8a4d768cc4b5915a19f9a3b87
Author: aaryanshukla <53713108+aaryanshukla at users.noreply.github.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M libc/config/darwin/arm/entrypoints.txt
M libc/config/darwin/x86_64/entrypoints.txt
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/arm/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/config/windows/entrypoints.txt
M libc/docs/math/index.rst
M libc/newhdrgen/yaml/math.yaml
M libc/spec/llvm_libc_ext.td
M libc/spec/stdc.td
M libc/src/math/CMakeLists.txt
A libc/src/math/fdiv.h
A libc/src/math/fdivf128.h
A libc/src/math/fdivl.h
A libc/src/math/ffma.h
A libc/src/math/ffmaf128.h
A libc/src/math/ffmal.h
M libc/src/math/generic/CMakeLists.txt
A libc/src/math/generic/fdiv.cpp
A libc/src/math/generic/fdivf128.cpp
A libc/src/math/generic/fdivl.cpp
A libc/src/math/generic/ffma.cpp
A libc/src/math/generic/ffmaf128.cpp
A libc/src/math/generic/ffmal.cpp
M libc/test/src/math/CMakeLists.txt
A libc/test/src/math/fdiv_test.cpp
A libc/test/src/math/fdivl_test.cpp
A libc/test/src/math/ffma_test.cpp
A libc/test/src/math/ffmal_test.cpp
M libc/test/src/math/smoke/CMakeLists.txt
M libc/test/src/math/smoke/DivTest.h
A libc/test/src/math/smoke/fdiv_test.cpp
A libc/test/src/math/smoke/fdivf128_test.cpp
A libc/test/src/math/smoke/fdivl_test.cpp
A libc/test/src/math/smoke/ffma_test.cpp
A libc/test/src/math/smoke/ffmaf128_test.cpp
A libc/test/src/math/smoke/ffmal_test.cpp
M libc/utils/MPFRWrapper/MPFRUtils.cpp
Log Message:
-----------
[libc][math][c23] Add ffma{,l,f128} and fdiv{,l,f128} C23 math functions #101089 (#101253)
- added all variations of ffma and fdiv
- will add all new headers into yaml for next patch
- only fsub is left then all basic operations for float is complete
---------
Co-authored-by: OverMighty <its.overmighty at gmail.com>
Commit: 31d4cd7393057b978141cda9151e3f59edab2b52
https://github.com/llvm/llvm-project/commit/31d4cd7393057b978141cda9151e3f59edab2b52
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M clang/docs/OpenMPSupport.rst
Log Message:
-----------
[Clang][Doc] Fix an error in `OpenMPSupport.rst`
Commit: ba227cb0d2c95ce315b843be000af45fcb976757
https://github.com/llvm/llvm-project/commit/ba227cb0d2c95ce315b843be000af45fcb976757
Author: Alexis Engelke <engelke at in.tum.de>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp
Log Message:
-----------
[CodeGen] Fix PreISelLowering not reporting changes (#102184)
expandVectorPredication may change code, even if the intrinsic itself
remains in the code. Report changes whenever such an intrinsic is
encountered, because code could have been changed.
Another follow-up fix for #101652 to fix expensive-checks-only failure.
Commit: 1e76486315d271cc126fe199902e21dae91fff64
https://github.com/llvm/llvm-project/commit/1e76486315d271cc126fe199902e21dae91fff64
Author: gonzalobg <65027571+gonzalobg at users.noreply.github.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTX.h
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXUtilities.h
M llvm/test/CodeGen/NVPTX/load-store-sm-70.ll
M llvm/test/CodeGen/NVPTX/load-store.ll
Log Message:
-----------
[NVPTX] Add Volta Atomic SequentiallyConsistent Load and Store Operations (#98551)
This PR Builds on #98022 .
It adds support for Volta's SequentiallyConsistent Load and Store
operations at system scope.
Commit: c086df864dbfa1e4a070c3344e72e744ab79c1b0
https://github.com/llvm/llvm-project/commit/c086df864dbfa1e4a070c3344e72e744ab79c1b0
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M libcxx/test/std/time/time.cal/time.cal.ymdlast/time.cal.ymdlast.nonmembers/comparisons.pass.cpp
Log Message:
-----------
[libc++][chrono][test] Fixes bogus loops. (#101890)
Changes the loop range to match similar tests and avoids zero
iterations. The original motivation to reduce the number of iterations
was to allow the test to be executed during constant evaluation.
Fixes: https://github.com/llvm/llvm-project/issues/100502
Commit: ac91c26c5e61e35c81f1560acb23bcbb72878030
https://github.com/llvm/llvm-project/commit/ac91c26c5e61e35c81f1560acb23bcbb72878030
Author: Sterling-Augustine <56981066+Sterling-Augustine at users.noreply.github.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/include/llvm/SandboxIR/SandboxIR.h
M llvm/lib/SandboxIR/SandboxIR.cpp
M llvm/unittests/SandboxIR/SandboxIRTest.cpp
M llvm/unittests/SandboxIR/TrackerTest.cpp
Log Message:
-----------
[SandboxIR] Implement missing PHINode functions (#101734)
replaceIncomingBlockWith and removeIncomingValueIf are both
straightforward and done.
I'll defer copyIncomingBlocks until a couple of other changes that also
handle blocks go in.
Commit: aebefb29a20ebb1e07342828bc99e330ced13a08
https://github.com/llvm/llvm-project/commit/aebefb29a20ebb1e07342828bc99e330ced13a08
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M libcxx/docs/Status/Cxx20Issues.csv
M libcxx/include/fstream
M libcxx/include/ios
M libcxx/include/sstream
M libcxx/include/string
M libcxx/test/std/input.output/file.streams/fstreams/fstream.cons/default.pass.cpp
M libcxx/test/std/input.output/file.streams/fstreams/fstream.cons/move.pass.cpp
M libcxx/test/std/input.output/file.streams/fstreams/fstream.cons/path.pass.cpp
M libcxx/test/std/input.output/file.streams/fstreams/fstream.cons/pointer.pass.cpp
M libcxx/test/std/input.output/file.streams/fstreams/fstream.cons/string.pass.cpp
M libcxx/test/std/input.output/file.streams/fstreams/ifstream.cons/default.pass.cpp
M libcxx/test/std/input.output/file.streams/fstreams/ifstream.cons/move.pass.cpp
M libcxx/test/std/input.output/file.streams/fstreams/ifstream.cons/path.pass.cpp
M libcxx/test/std/input.output/file.streams/fstreams/ifstream.cons/pointer.pass.cpp
M libcxx/test/std/input.output/file.streams/fstreams/ifstream.cons/string.pass.cpp
M libcxx/test/std/input.output/file.streams/fstreams/ofstream.cons/default.pass.cpp
M libcxx/test/std/input.output/file.streams/fstreams/ofstream.cons/move.pass.cpp
M libcxx/test/std/input.output/file.streams/fstreams/ofstream.cons/path.pass.cpp
M libcxx/test/std/input.output/file.streams/fstreams/ofstream.cons/pointer.pass.cpp
M libcxx/test/std/input.output/file.streams/fstreams/ofstream.cons/string.pass.cpp
M libcxx/test/std/input.output/iostreams.base/ios/basic.ios.members/copyfmt.pass.cpp
M libcxx/test/std/input.output/string.streams/istringstream/istringstream.cons/default.pass.cpp
M libcxx/test/std/input.output/string.streams/istringstream/istringstream.cons/mode.alloc.pass.cpp
M libcxx/test/std/input.output/string.streams/istringstream/istringstream.cons/move.pass.cpp
M libcxx/test/std/input.output/string.streams/istringstream/istringstream.cons/string-alloc.mode.pass.cpp
M libcxx/test/std/input.output/string.streams/istringstream/istringstream.cons/string.alloc.pass.cpp
M libcxx/test/std/input.output/string.streams/istringstream/istringstream.cons/string.mode.alloc.pass.cpp
M libcxx/test/std/input.output/string.streams/istringstream/istringstream.cons/string.move.mode.pass.cpp
M libcxx/test/std/input.output/string.streams/istringstream/istringstream.cons/string.pass.cpp
M libcxx/test/std/input.output/string.streams/ostringstream/ostringstream.cons/default.pass.cpp
M libcxx/test/std/input.output/string.streams/ostringstream/ostringstream.cons/mode.alloc.pass.cpp
M libcxx/test/std/input.output/string.streams/ostringstream/ostringstream.cons/move.pass.cpp
M libcxx/test/std/input.output/string.streams/ostringstream/ostringstream.cons/string-alloc.mode.pass.cpp
M libcxx/test/std/input.output/string.streams/ostringstream/ostringstream.cons/string.alloc.pass.cpp
M libcxx/test/std/input.output/string.streams/ostringstream/ostringstream.cons/string.mode.alloc.pass.cpp
M libcxx/test/std/input.output/string.streams/ostringstream/ostringstream.cons/string.move.mode.pass.cpp
M libcxx/test/std/input.output/string.streams/ostringstream/ostringstream.cons/string.pass.cpp
M libcxx/test/std/input.output/string.streams/stringstream/stringstream.cons/default.pass.cpp
M libcxx/test/std/input.output/string.streams/stringstream/stringstream.cons/mode.alloc.pass.cpp
M libcxx/test/std/input.output/string.streams/stringstream/stringstream.cons/move.pass.cpp
M libcxx/test/std/input.output/string.streams/stringstream/stringstream.cons/string-alloc.mode.pass.cpp
M libcxx/test/std/input.output/string.streams/stringstream/stringstream.cons/string.alloc.pass.cpp
M libcxx/test/std/input.output/string.streams/stringstream/stringstream.cons/string.mode.alloc.pass.cpp
M libcxx/test/std/input.output/string.streams/stringstream/stringstream.cons/string.move.mode.pass.cpp
M libcxx/test/std/input.output/string.streams/stringstream/stringstream.cons/string.pass.cpp
M libcxx/test/std/strings/basic.string/string.cons/move_alloc.pass.cpp
M libcxx/test/std/strings/basic.string/string.cons/substr_rvalue.pass.cpp
M libcxx/test/std/strings/basic.string/string.modifiers/string_swap/swap.pass.cpp
M libcxx/test/support/operator_hijacker.h
Log Message:
-----------
[libc++] Implements LWG3130. (#101889)
This adds addressof at the required places in [input.output]. Some of
the new tests failed since string used operator& internally. These have
been fixed too.
Note the new fstream tests perform output to a basic_string instead of a
double. Using a double requires num_get specialization
num_get<CharT, istreambuf_iterator<CharT,
char_traits_operator_hijacker<CharT>>
This facet is not present in the locale database so the conversion would
fail due to a missing locale facet. Using basic_string avoids using the
locale.
As a drive-by fixes several bugs in the ofstream.cons tests. These
tested ifstream instead of ofstream with an open mode.
Implements:
- LWG3130 [input.output] needs many addressof
Closes #100246.
Commit: 9a850d50771ae59bc3cf47429dd610230a64b50e
https://github.com/llvm/llvm-project/commit/9a850d50771ae59bc3cf47429dd610230a64b50e
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/lib/IR/ConstantRange.cpp
M llvm/test/Transforms/CorrelatedValuePropagation/shl.ll
M llvm/unittests/IR/ConstantRangeTest.cpp
Log Message:
-----------
[ConstantRange] Improve `shlWithNoWrap` (#101800)
Closes https://github.com/dtcxzyw/llvm-tools/issues/22.
Commit: a9dfa39dac974b20e78662eecb3b10ac8372cf43
https://github.com/llvm/llvm-project/commit/a9dfa39dac974b20e78662eecb3b10ac8372cf43
Author: Natan-GabrielTiutiuIntel <101411449+Natan-GabrielTiutiuIntel at users.noreply.github.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M mlir/include/mlir/Pass/PassRegistry.h
M mlir/include/mlir/Tools/mlir-opt/MlirOptMain.h
M mlir/lib/Pass/PassRegistry.cpp
M mlir/lib/Tools/mlir-opt/MlirOptMain.cpp
Log Message:
-----------
[mlir] Add --list-passes option to mlir-opt (#100420)
Currently, the only way to see the passes that were registered is by
calling “mlir-opt --help”. However, for compilers with 500+ passes, the
help message becomes too long and sometimes hard to understand. In this
PR I add a new "--list-passes" option to mlir-opt, which can be used for
printing only the registered passes, a feature that would be extremely
useful.
Commit: d634287eda50a84731a1366b7d79ff99722c7dad
https://github.com/llvm/llvm-project/commit/d634287eda50a84731a1366b7d79ff99722c7dad
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M libc/utils/gpu/loader/Loader.h
Log Message:
-----------
[libc] Fix GPU argument vector writing `nullptr` to string
Summary:
The intention behind this code was to null terminate the `envp` string,
but it accidentally went into the string data.
Commit: 07bd916bf913c28ca251fa8789812deca6f73418
https://github.com/llvm/llvm-project/commit/07bd916bf913c28ca251fa8789812deca6f73418
Author: Kevin Frei <freik at meta.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M lldb/include/lldb/Host/Config.h.cmake
M lldb/packages/Python/lldbsuite/test/decorators.py
M lldb/packages/Python/lldbsuite/test/make/Makefile.rules
M lldb/source/API/SBDebugger.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/SymbolLocator/CMakeLists.txt
M lldb/source/Plugins/SymbolVendor/ELF/SymbolVendorELF.cpp
A lldb/test/API/debuginfod/Normal/Makefile
A lldb/test/API/debuginfod/Normal/TestDebuginfod.py
A lldb/test/API/debuginfod/Normal/main.c
A lldb/test/API/debuginfod/SplitDWARF/Makefile
A lldb/test/API/debuginfod/SplitDWARF/TestDebuginfodDWP.py
A lldb/test/API/debuginfod/SplitDWARF/main.c
Log Message:
-----------
[lldb][debuginfod] Fix the DebugInfoD PR that caused issues when working with stripped binaries (#99362)
@walter-erquinigo found the the [PR with testing and a fix for
DebugInfoD](https://github.com/llvm/llvm-project/pull/98344) caused an
issue when working with stripped binaries.
The issue is that when you're working with split-dwarf, there are *3*
possible files: The stripped binary the user is debugging, the
"only-keep-debug" *or* unstripped binary, plus the `.dwp` file. The
debuginfod plugin should provide the unstripped/OKD binary. However, if
the debuginfod plugin fails, the default symbol locator plugin will just
return the stripped binary, which doesn't help. So, to address that, the
SymbolVendorELF code checks to see if the SymbolLocator's
ExecutableObjectFile request returned the same file, and bails if that's
the case. You can see the specific diff as the second commit in the PR.
I'm investigating adding a test: I can't quite get a simple repro, and
I'm unwilling to make any additional changes to Makefile.rules to this
diff, for Pavlovian reasons.
Commit: b1ae73172cf736e4c6549f936a90a6ce10b6f0c4
https://github.com/llvm/llvm-project/commit/b1ae73172cf736e4c6549f936a90a6ce10b6f0c4
Author: lntue <35648136+lntue at users.noreply.github.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M libc/src/math/generic/pow.cpp
M libc/test/src/math/pow_test.cpp
Log Message:
-----------
[libc][math] Improve the error analysis and accuracy for pow function. (#102098)
Commit: a77829c2ccf272ddec7449c743bc8106905e89cb
https://github.com/llvm/llvm-project/commit/a77829c2ccf272ddec7449c743bc8106905e89cb
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
A flang/include/flang/Runtime/CUDA/descriptor.h
M flang/lib/Optimizer/Transforms/CufOpConversion.cpp
M flang/runtime/CUDA/CMakeLists.txt
A flang/runtime/CUDA/descriptor.cpp
M flang/test/Fir/CUDA/cuda-allocate.fir
M flang/unittests/Runtime/CUDA/AllocatorCUF.cpp
Log Message:
-----------
[flang][cuda] Allocate local descriptor in managed memory (#102060)
This patch adds entry point in the runtime to be able to allocate
descriptors in managed memory. These entry points currently only call
`CUFAllocManaged` and `CUFFreeManaged` but could be more complicated in
the future.
`cuf.alloc` and `cuf.free` related to local descriptors are converted
into runtime calls.
Commit: 4763251eda9be20a4179eea49d3d4f1c972940af
https://github.com/llvm/llvm-project/commit/4763251eda9be20a4179eea49d3d4f1c972940af
Author: vporpo <vporpodas at google.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/include/llvm/SandboxIR/SandboxIR.h
M llvm/include/llvm/SandboxIR/SandboxIRValues.def
M llvm/include/llvm/SandboxIR/Tracker.h
M llvm/lib/SandboxIR/SandboxIR.cpp
M llvm/lib/SandboxIR/Tracker.cpp
M llvm/unittests/SandboxIR/SandboxIRTest.cpp
M llvm/unittests/SandboxIR/TrackerTest.cpp
Log Message:
-----------
[SandboxIR] Implement AllocaInst (#102027)
This patch implements sandboxir::AllocaInst which mirrors
llvm::AllocaInst.
Commit: 07d1ad4d18047018f33d3d306891c666d8a54fb3
https://github.com/llvm/llvm-project/commit/07d1ad4d18047018f33d3d306891c666d8a54fb3
Author: Andrzej Warzynski <andrzej.warzynski at arm.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M mlir/docs/Dialects/Vector.md
Log Message:
-----------
[mlir][vector] Fix link in docs (nfc)
Commit: ce5a044db019392185975e551b466ea4f43756af
https://github.com/llvm/llvm-project/commit/ce5a044db019392185975e551b466ea4f43756af
Author: Michael Liao <michael.hliao at gmail.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/test/CodeGen/M68k/pipeline.ll
Log Message:
-----------
[M68k] Fix compilation pipeline check
- After ExpandVP pass is merged into PreISelIntrinsicLowering
Commit: dbb77eb8708c05d2a94da5e8410f93af6416dbd0
https://github.com/llvm/llvm-project/commit/dbb77eb8708c05d2a94da5e8410f93af6416dbd0
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M libc/utils/gpu/loader/Loader.h
Log Message:
-----------
[libc] Fix index into argument vector
Commit: eef991635ff35a8c5f91e8d5a2c5fa81bfbba30d
https://github.com/llvm/llvm-project/commit/eef991635ff35a8c5f91e8d5a2c5fa81bfbba30d
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast.ll
M llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
Log Message:
-----------
[AMDGPU] Enable `AAAddressSpace` in `AMDGPUAttributor` (#101593)
Commit: eb91d747c16abfe9c1e70f47c18346fccaed88d9
https://github.com/llvm/llvm-project/commit/eb91d747c16abfe9c1e70f47c18346fccaed88d9
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
Log Message:
-----------
[Attributor] Improve debug string of `AAUnderlyingObjects` (#101861)
Commit: 4b8c1131b6521562d82d5694d146ab44479d175a
https://github.com/llvm/llvm-project/commit/4b8c1131b6521562d82d5694d146ab44479d175a
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/extractelement-phi-in-landingpad.ll
Log Message:
-----------
[SLP]Fix PR102187: do not insert extractelement before landingpad instruction.
Landingpad instruction must be the very first instruction after the phi
nodes, so need to inser extractelement/shuffles after this instruction.
Fixes https://github.com/llvm/llvm-project/issues/102187
Commit: fef716c577cfbe231b6299b395321fe2826f8e7b
https://github.com/llvm/llvm-project/commit/fef716c577cfbe231b6299b395321fe2826f8e7b
Author: Shoaib Meenai <smeenai at fb.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M clang/lib/CodeGen/CGVTables.cpp
M clang/test/CodeGenCXX/OmitRTTIComponentABI/simple-vtable-definition.cpp
M clang/test/CodeGenCXX/RelativeVTablesABI/child-inheritted-from-parent-in-comdat.cpp
M clang/test/CodeGenCXX/RelativeVTablesABI/cross-translation-unit-1.cpp
M clang/test/CodeGenCXX/RelativeVTablesABI/cross-translation-unit-2.cpp
M clang/test/CodeGenCXX/RelativeVTablesABI/diamond-inheritance.cpp
M clang/test/CodeGenCXX/RelativeVTablesABI/diamond-virtual-inheritance.cpp
M clang/test/CodeGenCXX/RelativeVTablesABI/inheritted-virtual-function.cpp
M clang/test/CodeGenCXX/RelativeVTablesABI/inline-virtual-function.cpp
M clang/test/CodeGenCXX/RelativeVTablesABI/multiple-inheritance.cpp
M clang/test/CodeGenCXX/RelativeVTablesABI/no-alias-when-dso-local.cpp
M clang/test/CodeGenCXX/RelativeVTablesABI/override-pure-virtual-method.cpp
M clang/test/CodeGenCXX/RelativeVTablesABI/overriden-virtual-function.cpp
M clang/test/CodeGenCXX/RelativeVTablesABI/relative-vtables-flag.cpp
M clang/test/CodeGenCXX/RelativeVTablesABI/relative-vtables-hwasan.cpp
M clang/test/CodeGenCXX/RelativeVTablesABI/simple-vtable-definition.cpp
Log Message:
-----------
[CodeGen] Make non-COMDAT relative vtable internal instead of private (#102056)
When using the relative vtable ABI, if a vtable is not dso_local, it's
given private linkage (if not COMDAT) or hidden visibility (if COMDAT)
to make it dso_local (to place it in rodata instead of data.rel.ro), and
an alias generated with the original linkage and visibility. This alias
could later be removed from the symbol table, e.g. if using a version
script, at which point we lose all symbol information about the vtable.
Use internal linkage instead of private linkage to avoid this.
While I'm here, clarify the comment about why COMDAT vtables can't use
internal (or private) linkage, and associate it with the else block
where hidden visibility is applied instead of internal linkage.
Commit: c8041db175aa8c55e986e5cde2106224c3aa1ce2
https://github.com/llvm/llvm-project/commit/c8041db175aa8c55e986e5cde2106224c3aa1ce2
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/include/llvm/BinaryFormat/COFF.h
M llvm/include/llvm/Object/COFF.h
M llvm/lib/Object/COFFObjectFile.cpp
A llvm/test/tools/llvm-readobj/COFF/arm64x-reloc-invalid.yaml
A llvm/test/tools/llvm-readobj/COFF/arm64x-reloc.yaml
M llvm/test/tools/yaml2obj/COFF/load-config.yaml
M llvm/tools/llvm-readobj/COFFDumper.cpp
Log Message:
-----------
[Object][COFF][llvm-readobj] Add support for ARM64X dynamic relocations. (#97229)
Commit: 560193841d51ff23ae5918cf6dab238d0575a428
https://github.com/llvm/llvm-project/commit/560193841d51ff23ae5918cf6dab238d0575a428
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/X86/landing_pad.ll
Log Message:
-----------
[SLP]Better sorting of phi instructions by comparing type sizes (#102188)
Currently SLP vectorizer compares phi instructions by the type id of the
compared instructions, which may failed in case of different integer
types,
with the different sizes. Patch adds comparison by type sizes to fix
this.
Commit: 8d21f1b8e0a45b2409c58d0ff2431d9f657e1c92
https://github.com/llvm/llvm-project/commit/8d21f1b8e0a45b2409c58d0ff2431d9f657e1c92
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/test/Transforms/Attributor/heap_to_stack_gpu.ll
M llvm/test/Transforms/Attributor/value-simplify-gpu.ll
M llvm/test/Transforms/OpenMP/barrier_removal.ll
M llvm/test/Transforms/PhaseOrdering/varargs.ll
Log Message:
-----------
AMDGPU: Fix using wrong alloca address space in test (#102108)
Commit: 171bbe995e59c6c04ee83a7fa22b9777349f1460
https://github.com/llvm/llvm-project/commit/171bbe995e59c6c04ee83a7fa22b9777349f1460
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/lib/Object/COFFObjectFile.cpp
Log Message:
-----------
[Object][COFF] Use uintptr_t for getRvaPtr call in Arm64XRelocRef::validate.
Fixes #97229.
Commit: 36772cf5994e8467d7a8a4f48b3d7fbead64d6d6
https://github.com/llvm/llvm-project/commit/36772cf5994e8467d7a8a4f48b3d7fbead64d6d6
Author: Martin Storsjö <martin at martin.st>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
M llvm/test/MC/ARM/Windows/branch-reloc-offset.s
Log Message:
-----------
[ARM] [Windows] Error out on branch relocations that require a symbol offset (#101906)
This adds the same kind of verification for ARM, as was added for
AArch64 in 1e7f592a890aad860605cf5220530b3744e107ba. This allows
catching issues at assembly time, instead of having the linker
misinterpret the relocations (as the linker ignores the symbol offset).
This verifies that the issue fixed by
8dd065d5bc81b0c8ab57f365bb169a5d92928f25 really is fixed, and points out
explicitly if the same issue appears elsewhere.
Note that the parameter Value in the adjustFixupValue function is offset
by 4 from the value that is stored as immediate in the instructions, so
we compare with 4, when we want to make sure that the written immediate
will be zero.
Commit: 222207eccdf15cc5d55ed3d713ff0b899d6d9c37
https://github.com/llvm/llvm-project/commit/222207eccdf15cc5d55ed3d713ff0b899d6d9c37
Author: Rose Silicon <gfunni234 at gmail.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
Log Message:
-----------
[InstCombine] (NFC) Remove improper TODO for a - UMIN (#101076)
It is already handled in a different method, especially as a - UMIN(a,
b) cannot be handled by a select statement, unless it means something
like: "(c < b) ? b - ((b > c) ? c : b) : 0;" but LLVM handles that case
as well.
Commit: f6ea4a350ea6f452966733aefe46184e79b6d9a4
https://github.com/llvm/llvm-project/commit/f6ea4a350ea6f452966733aefe46184e79b6d9a4
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M lldb/source/Plugins/ExpressionParser/Clang/ClangASTImporter.cpp
M lldb/source/Plugins/ExpressionParser/Clang/ClangASTImporter.h
M lldb/source/Plugins/ExpressionParser/Clang/ClangUserExpression.cpp
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCDeclVendor.cpp
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.h
M lldb/unittests/Symbol/TestClangASTImporter.cpp
Log Message:
-----------
[lldb][TypeSystemClang] Pass ClangASTMetadata around by value (#102161)
This patch changes the return type of `GetMetadata` from a
`ClangASTMetadata*` to a `std::optional<ClangASTMetadata>`. Except for
one call-site (`SetDeclIsForcefullyCompleted`), we never actually make
use of the mutability of the returned metadata. And we never make use of
the pointer-identity. By passing `ClangASTMetadata` by-value (the type
is fairly small, size of 2 64-bit pointers) we'll avoid some questions
surrounding the lifetimes/ownership/mutability of this metadata.
For consistency, we also change the parameter to `SetMetadata` from
`ClangASTMetadata&` to `ClangASTMetadata` (which is an NFC since we copy
the data anyway).
This came up during some changes we plan to make where we [create
redeclaration chains for decls in the LLDB
AST](https://github.com/llvm/llvm-project/pull/95100). We want to avoid
having to dig out the canonical decl of the declaration chain for
retrieving/setting the metadata. It should just be copied across all
decls in the chain. This is easier to guarantee when everything is done
by-value.
Commit: 53596195c201d37a5dd3d1031d86e872afda961b
https://github.com/llvm/llvm-project/commit/53596195c201d37a5dd3d1031d86e872afda961b
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M flang/include/flang/Runtime/CUDA/allocator.h
M flang/include/flang/Runtime/CUDA/descriptor.h
M flang/lib/Optimizer/Transforms/CufOpConversion.cpp
M flang/runtime/CUDA/allocator.cpp
M flang/runtime/CUDA/descriptor.cpp
M flang/unittests/Runtime/CUDA/AllocatorCUF.cpp
Log Message:
-----------
[flang][cuda][NFC] Disambiguate namespace with cuf dialect (#102194)
Rename namespace `Fortran::runtime::cuf` to `Fortran::runtime::cuda` to
avoid embiguity with the namespace `::cuf` that is defined in the CUF
dialect.
Commit: 652d393e137af5c9ef1b9afdcc383725415bc13a
https://github.com/llvm/llvm-project/commit/652d393e137af5c9ef1b9afdcc383725415bc13a
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M flang/include/flang/Runtime/CUDA/allocator.h
M flang/include/flang/Runtime/allocator-registry.h
M flang/lib/Lower/ConvertVariable.cpp
M flang/runtime/CUDA/allocator.cpp
Log Message:
-----------
[flang][cuda] Defined allocator for unified data (#102189)
CUDA unified variable where set to use the same allocator than managed
variable. This patch adds a specific allocator for the unified
variables. Currently it will call the managed allocator underneath but
we want to have the flexibility to change that in the future.
Commit: dcd3190e1406ceb5bc44e904cb8e7a5f5f93bb77
https://github.com/llvm/llvm-project/commit/dcd3190e1406ceb5bc44e904cb8e7a5f5f93bb77
Author: Han-Chung Wang <hanhan0912 at gmail.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
M mlir/test/Dialect/Linalg/vectorize-tensor-extract.mlir
Log Message:
-----------
Revert "[mlir][linalg] Relax tensor.extract vectorization" (#102232)
Reverts llvm/llvm-project#99299 because it breaks the lowering. To
repro: `mlir-opt -transform-interpreter ~/repro.mlir`
```mlir
#map = affine_map<(d0, d1) -> (d0)>
#map1 = affine_map<(d0, d1) -> (d1)>
#map2 = affine_map<(d0, d1) -> (d0, d1)>
#map3 = affine_map<(d0, d1) -> (d0 + d1)>
module {
func.func @foo(%arg0: index, %arg1: tensor<2xf32>, %arg2: tensor<4xf32>, %arg3: tensor<1xf32>) -> tensor<4x1xf32> {
%c0 = arith.constant 0 : index
%cst = arith.constant 1.000000e+00 : f32
%cst_0 = arith.constant 0.000000e+00 : f32
%0 = tensor.empty() : tensor<4x1xf32>
%1 = linalg.generic {indexing_maps = [#map, #map1, #map2], iterator_types = ["parallel", "parallel"]} ins(%arg2, %arg3 : tensor<4xf32>, tensor<1xf32>) outs(%0 : tensor<4x1xf32>) {
^bb0(%in: f32, %in_1: f32, %out: f32):
%2 = linalg.index 0 : index
%3 = linalg.index 1 : index
%4 = affine.apply #map3(%3, %arg0)
%extracted = tensor.extract %arg1[%c0] : tensor<2xf32>
%5 = arith.cmpi eq, %2, %c0 : index
%6 = arith.cmpi ult, %2, %c0 : index
%7 = arith.select %5, %cst, %in : f32
%8 = arith.select %6, %cst_0, %7 : f32
%9 = arith.cmpi eq, %4, %c0 : index
%10 = arith.cmpi ult, %4, %c0 : index
%11 = arith.select %9, %cst, %in_1 : f32
%12 = arith.select %10, %cst_0, %11 : f32
%13 = arith.mulf %8, %12 : f32
%14 = arith.mulf %13, %extracted : f32
%15 = arith.cmpi eq, %2, %4 : index
%16 = arith.select %15, %cst, %cst_0 : f32
%17 = arith.subf %16, %14 : f32
linalg.yield %17 : f32
} -> tensor<4x1xf32>
return %1 : tensor<4x1xf32>
}
}
module attributes {transform.with_named_sequence} {
transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) {
%0 = transform.structured.match ops{["linalg.generic"]} in %arg1 : (!transform.any_op) -> !transform.any_op
transform.structured.vectorize %0 : !transform.any_op
transform.yield
}
}
```
Commit: 1d7e8d390278ede971d8200391051a646947c32f
https://github.com/llvm/llvm-project/commit/1d7e8d390278ede971d8200391051a646947c32f
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
A llvm/test/TableGen/SubtargetFeatureUniqueNames.td
M llvm/utils/TableGen/SubtargetEmitter.cpp
Log Message:
-----------
[TableGen] Emit better error message for duplicate Subtarget features. (#102090)
- Keep track of last definition of a feature in a `DenseMap` and use
it to report a better error message when a duplicate feature is found.
- Use StringMap instead of a std::map in `EmitStageAndOperandCycleData`
- Add a unit test to check if duplicate names are flagged.
Commit: 748d85319613f8887a66e1ba45f4e92cf0b83fb4
https://github.com/llvm/llvm-project/commit/748d85319613f8887a66e1ba45f4e92cf0b83fb4
Author: Mircea Trofin <mtrofin at google.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/include/llvm/ProfileData/PGOCtxProfReader.h
M llvm/lib/ProfileData/PGOCtxProfReader.cpp
M llvm/unittests/ProfileData/PGOCtxProfReaderWriterTest.cpp
Log Message:
-----------
[nfc][ctx_prof] Rename `PGOContextualProfile` to `PGOCtxProfContext` (#102209)
Commit: 5dc9c896e43c9614ccf313f4ffcd0690eeebd1ac
https://github.com/llvm/llvm-project/commit/5dc9c896e43c9614ccf313f4ffcd0690eeebd1ac
Author: Sam Clegg <sbc at chromium.org>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M lld/test/wasm/lto/stub-library.s
M lld/wasm/Driver.cpp
M lld/wasm/InputFiles.cpp
Log Message:
-----------
[lld][WebAssembly] Fix stub library deps causing LTO archive members to be required post-LTO (#101894)
Fixes: https://github.com/emscripten-core/emscripten/issues/16836
Commit: e1c04795bb500793dc0a23354c7aadcc25fa7653
https://github.com/llvm/llvm-project/commit/e1c04795bb500793dc0a23354c7aadcc25fa7653
Author: Kelvin Li <kkwli at users.noreply.github.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M flang/lib/Optimizer/CodeGen/FIROpPatterns.cpp
M flang/test/Fir/box-typecode.fir
M flang/test/Fir/convert-to-llvm.fir
M flang/test/Fir/polymorphic.fir
M flang/test/Fir/tbaa.fir
M flang/test/Lower/allocatable-polymorphic.f90
Log Message:
-----------
[flang] Match the type of the element size in the box in getValueFromBox (#100512)
Currently, `%17 = fir.box_elesize %16 :
(!fir.class<!fir.ptr<!fir.type<_QFTt{a:i32,b:i32}>>>) -> i32`
is translated to
```
%4 = getelementptr { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] }, ptr %1, i32 0, i32 1
%5 = load i32, ptr %4, align 4
```
The type of the element size is `i64`. The load essentially truncates
the value and yields incorrect result in the big endian environment. The
problem occurs in the `storage_size` intrinsic on a polymorphic
variable.
Commit: 25cf3286427d2e3d3871edaaaa66fb937499052c
https://github.com/llvm/llvm-project/commit/25cf3286427d2e3d3871edaaaa66fb937499052c
Author: weiguozhi <57237827+weiguozhi at users.noreply.github.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/include/llvm/CodeGen/TargetFrameLowering.h
M llvm/lib/CodeGen/CFIInstrInserter.cpp
M llvm/lib/CodeGen/PrologEpilogInserter.cpp
M llvm/lib/Target/X86/X86FrameLowering.cpp
M llvm/lib/Target/X86/X86FrameLowering.h
M llvm/test/CodeGen/X86/apx/push2-pop2-vector-register.ll
M llvm/test/CodeGen/X86/apx/push2-pop2.ll
M llvm/test/CodeGen/X86/apx/pushp-popp.ll
M llvm/test/CodeGen/X86/avx512-intel-ocl.ll
A llvm/test/CodeGen/X86/clobber_base_ptr.ll
A llvm/test/CodeGen/X86/clobber_frame_ptr.ll
A llvm/test/CodeGen/X86/clobber_frame_ptr_x32.ll
M llvm/test/CodeGen/X86/i386-baseptr.ll
M llvm/test/CodeGen/X86/inline-asm-function-call-pic.ll
M llvm/test/CodeGen/X86/x86-32-intrcc.ll
M llvm/test/CodeGen/X86/x86-64-baseptr.ll
M llvm/test/CodeGen/X86/x86-64-flags-intrinsics.ll
Log Message:
-----------
Spill/restore FP/BP around instructions in which they are clobbered (#81048)
This patch fixes https://github.com/llvm/llvm-project/issues/17204.
If a base pointer is used in a function, and it is clobbered by an
instruction (typically an inline asm), current register allocator can't
handle this situation, so BP becomes garbage after those instructions.
It can also occur to FP in theory.
We can spill and reload FP/BP registers around those instructions. But
normal spill/reload instructions also use FP/BP, so we can't spill them
into normal spill slots, instead we spill them into the top of stack by
using SP register.
Commit: 8d0e3bfce13e29e418d92759d8ab152800405e04
https://github.com/llvm/llvm-project/commit/8d0e3bfce13e29e418d92759d8ab152800405e04
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/test/MC/AMDGPU/gfx10_asm_vop1.s
M llvm/test/MC/AMDGPU/gfx10_err_pos.s
M llvm/test/MC/AMDGPU/gfx12_asm_smem.s
Log Message:
-----------
[AMDGPU] Add parseStringOrIntWithPrefix helper in asm parser (#102213)
When we have a modifier with a value (like dst_sel:DWORD for example) we
only accept symbolic values. SP3 allows to use numberic constants as
well. Adding a helper function to allow both.
Besides the compatibility it is easier to use.
Commit: 6f484bbfbf916ea8d79ead82bcad2c9ce2ae69c0
https://github.com/llvm/llvm-project/commit/6f484bbfbf916ea8d79ead82bcad2c9ce2ae69c0
Author: Amir Ayupov <aaupov at fb.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M bolt/lib/Core/BinaryFunction.cpp
Log Message:
-----------
[BOLT] Turn non-empty CFI StateStack assert into a warning (#102216)
clang-15 can produce binaries with mismatched RememberState/RestoreState
CFIs. This is benign for unwinding, so replace an assert with a warning.
Commit: e243ca3ab218e96a40c7fa79b99dc1f69b0fb08e
https://github.com/llvm/llvm-project/commit/e243ca3ab218e96a40c7fa79b99dc1f69b0fb08e
Author: Sirraide <aeternalmail at gmail.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/TreeTransform.h
M clang/test/SemaTemplate/address_space-dependent.cpp
Log Message:
-----------
[Clang] Fix crash when transforming a `DependentAddressSpaceType` (#102206)
We were forgetting to pass the `TypeLocBuilder` along to
`TransformType`, causing us to complain if we then tried to build a
`DependentAddressSpaceTypeLoc` because the inner `TypeLoc` was
missing from the TLB.
Fixes #101685.
Commit: 79582bceb596b8d8d821acb956dbbbb3eb73727d
https://github.com/llvm/llvm-project/commit/79582bceb596b8d8d821acb956dbbbb3eb73727d
Author: Snehasish Kumar <snehasishk at google.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/include/llvm/Analysis/TargetLibraryInfo.def
M llvm/lib/Analysis/TargetLibraryInfo.cpp
M llvm/test/tools/llvm-tli-checker/ps4-tli-check.yaml
M llvm/unittests/Analysis/TargetLibraryInfoTest.cpp
Log Message:
-----------
Add __size_returning_new variant detection to TLI. (#101564)
Add support to detect __size_returning_new variants defined inproposal
P0901R5 to extend to operator new, see
http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2019/p0901r5.html for
details.
This PR matches the declarations exported by tcmalloc in
https://github.com/google/tcmalloc/blob/f2516691d01051defc558679f37720bba88d9862/tcmalloc/malloc_extension.h#L707-L711
Commit: 3cbad2d82a2fdbb49bf2cbd8185f9403cf4acbb1
https://github.com/llvm/llvm-project/commit/3cbad2d82a2fdbb49bf2cbd8185f9403cf4acbb1
Author: jeffreytan81 <jeffreytan at meta.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M lldb/include/lldb/Target/ThreadPlanSingleThreadTimeout.h
M lldb/include/lldb/Target/TimeoutResumeAll.h
M lldb/source/Target/ThreadPlanSingleThreadTimeout.cpp
Log Message:
-----------
Fix ASAN failure in TestSingleThreadStepTimeout.py (#102208)
This PR fixes the ASAN failure in
https://github.com/llvm/llvm-project/pull/90930.
The original PR made the assumption that parent
`ThreadPlanStepOverRange`'s lifetime will always be longer than
`ThreadPlanSingleThreadTimeout` leaf plan so it passes the
`m_timeout_info` as reference to it.
>From the ASAN failure, it seems that this assumption may not be true
(likely the thread stack is holding a strong reference to the leaf
plan).
This PR fixes this lifetime issue by using shared pointer instead of
passing by reference.
---------
Co-authored-by: jeffreytan81 <jeffreytan at fb.com>
Commit: 18bc9a94d3ec036bba5f14d3e355909e4d1588d3
https://github.com/llvm/llvm-project/commit/18bc9a94d3ec036bba5f14d3e355909e4d1588d3
Author: yonghong-song <yhs at fb.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/lib/Object/ELFObjectFile.cpp
M llvm/test/CodeGen/BPF/objdump_atomics.ll
M llvm/test/CodeGen/BPF/objdump_cond_op.ll
M llvm/test/CodeGen/BPF/objdump_imm_hex.ll
M llvm/test/CodeGen/BPF/objdump_static_var.ll
M llvm/test/MC/BPF/insn-unit.s
M llvm/test/MC/BPF/load-store-32.s
Log Message:
-----------
[BPF] Make llvm-objdump disasm default cpu v4 (#102166)
Currently, with the following example,
$ cat t.c
void foo(int a, _Atomic int *b)
{
*b &= a;
}
$ clang --target=bpf -O2 -c -mcpu=v3 t.c
$ llvm-objdump -d t.o
t.o: file format elf64-bpf
Disassembly of section .text:
0000000000000000 <foo>:
0: c3 12 00 00 51 00 00 00 <unknown>
1: 95 00 00 00 00 00 00 00 exit
Basically, the default cpu for llvm-objdump is v1 and it won't be able
to decode insn properly.
If we add --mcpu=v3 to llvm-objdump command line, we will have
$ llvm-objdump -d --mcpu=v3 t.o
t.o: file format elf64-bpf
Disassembly of section .text:
0000000000000000 <foo>:
0: c3 12 00 00 51 00 00 00 w1 = atomic_fetch_and((u32 *)(r2 + 0x0), w1)
1: 95 00 00 00 00 00 00 00 exit
The atomic_fetch_and insn can be decoded properly. Using latest cpu
version --mcpu=v4 can also decode properly like the above --mcpu=v3.
To avoid the above '<unknown>' decoding with common 'llvm-objdump -d
t.o', this patch marked the default cpu for llvm-objdump with the
current highest cpu number v4 in ELFObjectFileBase::tryGetCPUName(). The
cpu number in ELFObjectFileBase::tryGetCPUName() will be adjusted in the
future if cpu number is increased e.g. v5 etc. Such an approach also
aligns with gcc-bpf as discussed in [1].
Six bpf unit tests are affected with this change. I changed test output
for three unit tests and added --mcpu=v1 for the other three unit tests,
to demonstrate the default (cpu v4) behavior and explicit --mcpu=v1
behavior.
[1]
https://lore.kernel.org/bpf/6f32c0a1-9de2-4145-92ea-be025362182f@linux.dev/T/#m0f7e63c390bc8f5a5523e7f2f0537becd4205200
Co-authored-by: Yonghong Song <yonghong.song at linux.dev>
Commit: f731f9ca7b28243363bde77197b6ad259588ae93
https://github.com/llvm/llvm-project/commit/f731f9ca7b28243363bde77197b6ad259588ae93
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
A llvm/test/CodeGen/AMDGPU/indirect-call-set-from-other-function.ll
Log Message:
-----------
[Attributor] Fix an issue that an access is skipped by mistake (#101862)
When we check if an access can be skipped, there is a case that an
inter-procedural interference access exists after a dominant write.
Currently we
rely on `AAInterFnReachability` to tell if the access can be reachable.
If it is
not, we can safely skip the access. However, it is based on an
assumption that
the AA exists. It is possible that the AA doesn't exist. In this case,
we can't
safely assume the acess can be skipped because we have to assume the
access can
reach. This can happen when `AAInterFnReachability` is not in the
allowed AA
list when creating the attributor, such as AMDGPUAttributor.
Co-authored-by: Mark de Wever <koraq at xs4all.nl>
Commit: d93f6f92e3717f32d675de36cc45c9bf7d92f316
https://github.com/llvm/llvm-project/commit/d93f6f92e3717f32d675de36cc45c9bf7d92f316
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
R clang/test/Driver/linker-wrapper-passes.c
M clang/test/lit.cfg.py
M clang/test/lit.site.cfg.py.in
Log Message:
-----------
Revert "[LinkerWrapper] Extend with usual pass options (#96704)" (#102226)
This reverts commit 90ccf2187332ff900d46a58a27cb0353577d37cb.
Fixes: https://github.com/llvm/llvm-project/issues/100212
Commit: 5d33995dd15e0c4ab8cc77bc7faa59055534024e
https://github.com/llvm/llvm-project/commit/5d33995dd15e0c4ab8cc77bc7faa59055534024e
Author: Nico Weber <thakis at chromium.org>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/utils/gn/secondary/lldb/include/lldb/Host/BUILD.gn
Log Message:
-----------
[gn] port e77ac42bccb8
Commit: 735f849f370dae05413cdca4d311ba01e6e87187
https://github.com/llvm/llvm-project/commit/735f849f370dae05413cdca4d311ba01e6e87187
Author: Nico Weber <thakis at chromium.org>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/utils/gn/secondary/clang/test/BUILD.gn
Log Message:
-----------
Revert "[gn build] Manually port 90ccf21"
This reverts commit 46307f1a84bf832f32938c8ad2dc0605441a5319.
90ccf21 was reverted in 030ee841a9c.
Commit: 38c3b6a84880450b1515d140ba7902671ea0a3b0
https://github.com/llvm/llvm-project/commit/38c3b6a84880450b1515d140ba7902671ea0a3b0
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/include/llvm/Transforms/IPO/Attributor.h
M llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
M llvm/lib/Transforms/IPO/Attributor.cpp
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
M llvm/test/CodeGen/AMDGPU/direct-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/duplicate-attribute-indirect.ll
A llvm/test/CodeGen/AMDGPU/simple-indirect-call-2.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
Log Message:
-----------
Reapply "[Attributor][AMDGPU] Enable AAIndirectCallInfo for AMDAttributor (#100952)"
This reverts commit 874cd100a076f3b98aaae09f90ef224682501538.
Commit: 6d1e8181df9daa796e2742ee9a48ae20da73f725
https://github.com/llvm/llvm-project/commit/6d1e8181df9daa796e2742ee9a48ae20da73f725
Author: tcwzxx <tcwzxx at gmail.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/X86/stores_mix_sizes.ll
Log Message:
-----------
[SLP] The order of store chains needs to consider the size of the values. (#101810)
When store chains have the same value type ID and pointer type ID, they
may mix different sizes of values, such as i8 and i64. This can lead to
missed vectorization opportunities.
Commit: 894ab9de6d109ffb9aba46494fc619e78d5d365b
https://github.com/llvm/llvm-project/commit/894ab9de6d109ffb9aba46494fc619e78d5d365b
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll
Log Message:
-----------
[RISCV] Limit (and (sra x, c2), c1) -> (srli (srai x, c2-c3), c3) isel in some cases. (#102034)
If x is a shl by 32 and c1 is an simm12, we would prefer to use a
SRAIW+ANDI. This prevents selecting the slli to a separate slli
instruction.
Fixes regression from #101868
Commit: a87cb7a0038d4f0058f066e81e4ed7f0f4c540b5
https://github.com/llvm/llvm-project/commit/a87cb7a0038d4f0058f066e81e4ed7f0f4c540b5
Author: Ding Fei <fding at feysh.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M clang/lib/AST/ASTImporter.cpp
M clang/unittests/AST/ASTImporterTest.cpp
Log Message:
-----------
[clang][ASTImporter] Remove trailing return testing on lambda proto (#101031)
Lambdas without trailing return could also have return type defined
inside its body.
This fixes crashes (infinite recursion) on lambda expr without
parameters (no parentheses).
Commit: c703daf0a23ee9d952c2ea5db8da66fd6c28ea85
https://github.com/llvm/llvm-project/commit/c703daf0a23ee9d952c2ea5db8da66fd6c28ea85
Author: Ding Fei <fding at feysh.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M clang/lib/AST/ASTImporter.cpp
M clang/unittests/AST/ASTImporterTest.cpp
Log Message:
-----------
[clang][ASTImporter] support import return with UnaryTransformType (#101517)
This fixes infinite recursion crash on return with UnaryTransformType,
whose underlying type is a SubstTemplateTypeParmType which is
associated with current imported function.
Commit: daecf1f969557a4112bf96e4a3d548f6485cf7b8
https://github.com/llvm/llvm-project/commit/daecf1f969557a4112bf96e4a3d548f6485cf7b8
Author: Florian Mayer <fmayer at google.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M compiler-rt/lib/hwasan/hwasan.h
Log Message:
-----------
[compiler-rt] [HWASan] leave BufferedStackTrace uninit (#102247)
Otherwise we have to memset 2040 bytes (255 * 8) for each call to a
malloc-like function.
This caused noticable slowdown on AOSP.
Commit: c23f23668eb89beaff5ebcbb3eeaacafd5014d0d
https://github.com/llvm/llvm-project/commit/c23f23668eb89beaff5ebcbb3eeaacafd5014d0d
Author: Simon Tatham <simon.tatham at arm.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M libc/src/time/mktime.cpp
M libc/test/src/time/mktime_test.cpp
Log Message:
-----------
[libc] Fix overflow check for 32-bit mktime. (#101993)
The 32-bit time_t rolls over to a value with its high bit set at
2038-01-19 03:14:07. The overflow check for this in mktime() was
checking each individual component of the time: reject if year>2038, or
if month>1, or if day>19, etc. As a result it would reject valid times
before the overflow point, because a low-order component was out of
range even though a higher-order one makes the time as a whole safe. The
earliest failing value is 2145916808 == 2038-01-01 00:00:08, in which
only the seconds field 'overflows'.
Fixed so that if any component is _less_ than its threshold value, we
don't check the lower-order components.
Commit: 8ee43c060829fbe0170f6351b2a5dd3e23b24271
https://github.com/llvm/llvm-project/commit/8ee43c060829fbe0170f6351b2a5dd3e23b24271
Author: Schrodinger ZHU Yifan <yifanzhu at rochester.edu>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/api.td
M libc/docs/dev/undefined_behavior.rst
M libc/include/CMakeLists.txt
M libc/include/llvm-libc-types/CMakeLists.txt
A libc/include/llvm-libc-types/pthread_spinlock_t.h
M libc/newhdrgen/yaml/pthread.yaml
M libc/spec/posix.td
M libc/src/__support/threads/spin_lock.h
M libc/src/pthread/CMakeLists.txt
A libc/src/pthread/pthread_spin_destroy.cpp
A libc/src/pthread/pthread_spin_destroy.h
A libc/src/pthread/pthread_spin_init.cpp
A libc/src/pthread/pthread_spin_init.h
A libc/src/pthread/pthread_spin_lock.cpp
A libc/src/pthread/pthread_spin_lock.h
A libc/src/pthread/pthread_spin_trylock.cpp
A libc/src/pthread/pthread_spin_trylock.h
A libc/src/pthread/pthread_spin_unlock.cpp
A libc/src/pthread/pthread_spin_unlock.h
M libc/test/integration/src/pthread/CMakeLists.txt
M libc/test/integration/src/pthread/pthread_rwlock_test.cpp
A libc/test/integration/src/pthread/pthread_spinlock_test.cpp
Log Message:
-----------
[libc] add spin lock family functions (#100509)
This PR:
- add entrypoints for `pthread_spin_*`
- additionally, the fixes a typo that has been disabling lock related
tests
Commit: 8ba324586d141cdfa9563c3acec3543a20ebb4f3
https://github.com/llvm/llvm-project/commit/8ba324586d141cdfa9563c3acec3543a20ebb4f3
Author: Julius Alexandre <juliuswoosebert at gmail.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/include/llvm/SandboxIR/SandboxIR.h
M llvm/include/llvm/SandboxIR/SandboxIRValues.def
M llvm/lib/SandboxIR/SandboxIR.cpp
M llvm/unittests/SandboxIR/SandboxIRTest.cpp
Log Message:
-----------
[SandboxIR] Implement UnreachableInst (#101856)
This patch implements the `UnreachableInst` instruction in SandboxIR. Mirroring `llvm::UnreachableInst`.
Commit: 38c73f8afc7abf4c6912d4e56230dfaebe80cfdd
https://github.com/llvm/llvm-project/commit/38c73f8afc7abf4c6912d4e56230dfaebe80cfdd
Author: Julius Alexandre <juliuswoosebert at gmail.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/lib/SandboxIR/SandboxIR.cpp
Log Message:
-----------
[SandboxIR][NFC] Add missing getTopmostLLVMInstruction() (#102266)
`getTopmostLLVMInstruction()` was missing in a couple of places, this patch made sure to add them.
Commit: 20c158095e270f09fa3717ff7c68a5cfa08d1762
https://github.com/llvm/llvm-project/commit/20c158095e270f09fa3717ff7c68a5cfa08d1762
Author: Alexis Engelke <engelke at in.tum.de>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/include/llvm/CodeGen/MachineRegisterInfo.h
M llvm/lib/CodeGen/MachineRegisterInfo.cpp
M llvm/lib/CodeGen/TargetRegisterInfo.cpp
M llvm/tools/llvm-reduce/ReducerWorkItem.cpp
M llvm/tools/llvm-reduce/deltas/ReduceVirtualRegisters.cpp
Log Message:
-----------
[CodeGen] Allocate RegAllocHints map lazily (#102186)
This hint map is not required whenever a new register is added, in fact,
at -O0, it is not used at all. Growing this map is quite expensive, as
SmallVectors are not trivially copyable.
Grow this map only when hints are actually added to avoid multiple grows
and grows when no hints are added at all.
Commit: 08ad7eeffaa9568dabcadef72f2216e77bb789d0
https://github.com/llvm/llvm-project/commit/08ad7eeffaa9568dabcadef72f2216e77bb789d0
Author: cceerczw <chengzhiwei6 at huawei.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuffle-splat.mir
Log Message:
-----------
[AArch64] Fix MatchDup Lane Out Of Range In AArch64 (#101275)
The original code is intended to process pattern which ISEL generated.
The purpose of this pattern is duplicate a scalar value to vector
register which behavior like AArch64's Dup Inst.
See Url https://reviews.llvm.org/D81979 &&
https://reviews.llvm.org/D81221
The current code considers only the preceding situation which just
duplicate from Shuffle's LHS but does not consider the user code. RHS
should be considered.
Commit: 06a8fb0e18e1fd9663eca3b8446b83b7ab228b0e
https://github.com/llvm/llvm-project/commit/06a8fb0e18e1fd9663eca3b8446b83b7ab228b0e
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/test/CodeGen/WebAssembly/offset.ll
Log Message:
-----------
[SDAG] Transfer gep nusw/nuw to SDAG
The resulting add is nuw if either the gep was nuw or it was
nusw+nneg. Previously only inbounds+nneg was handled.
Test via wasm load offsets, which seems to most directly expose
these SDAG flags.
Commit: a9e2516c70b8ed6557ceb8b77ed4c966d79b9ad5
https://github.com/llvm/llvm-project/commit/a9e2516c70b8ed6557ceb8b77ed4c966d79b9ad5
Author: sinan <sinan.lin at linux.alibaba.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M bolt/lib/Rewrite/RewriteInstance.cpp
A bolt/test/X86/dynamic-relocs-on-entry.s
Log Message:
-----------
[BOLT] Support map other function entry address (#101466)
Allow BOLT to map the old address to a new binary address if the old
address is the entry of the function.
Commit: 98f7b6255950f9631bdb670d5318e32a0c62ed58
https://github.com/llvm/llvm-project/commit/98f7b6255950f9631bdb670d5318e32a0c62ed58
Author: Giuseppe Rossini <giuseppe.rossini at amd.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M mlir/lib/Dialect/Bufferization/Transforms/BufferDeallocationSimplification.cpp
M mlir/lib/Transforms/Utils/RegionUtils.cpp
M mlir/test/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation/dealloc-branchop-interface.mlir
M mlir/test/Dialect/Linalg/detensorize_entry_block.mlir
M mlir/test/Dialect/Linalg/detensorize_if.mlir
M mlir/test/Dialect/Linalg/detensorize_while.mlir
M mlir/test/Dialect/Linalg/detensorize_while_impure_cf.mlir
M mlir/test/Dialect/Linalg/detensorize_while_pure_cf.mlir
M mlir/test/Transforms/canonicalize-block-merge.mlir
M mlir/test/Transforms/canonicalize-dce.mlir
M mlir/test/Transforms/make-isolated-from-above.mlir
A mlir/test/Transforms/test-canonicalize-merge-large-blocks.mlir
Log Message:
-----------
[mlir] Fix block merging (#102038)
With this PR I am trying to address:
https://github.com/llvm/llvm-project/issues/63230.
What changed:
- While merging identical blocks, don't add a block argument if it is
"identical" to another block argument. I.e., if the two block arguments
refer to the same `Value`. The operations operands in the block will
point to the argument we already inserted. This needs to happen to all
the arguments we pass to the different successors of the parent block
- After merged the blocks, get rid of "unnecessary" arguments. I.e., if
all the predecessors pass the same block argument, there is no need to
pass it as an argument.
- This last simplification clashed with
`BufferDeallocationSimplification`. The reason, I think, is that the two
simplifications are clashing. I.e., `BufferDeallocationSimplification`
contains an analysis based on the block structure. If we simplify the
block structure (by merging and/or dropping block arguments) the
analysis is invalid . The solution I found is to do a more prudent
simplification when running that pass.
**Note-1**: I ran all the integration tests
(`-DMLIR_INCLUDE_INTEGRATION_TESTS=ON`) and they passed.
**Note-2**: I fixed a bug found by @Dinistro in #97697 . The issue was
that, when looking for redundant arguments, I was not considering that
the block might have already some arguments. So the index (in the block
args list) of the i-th `newArgument` is `i+numOfOldArguments`.
Commit: 27d2d8919133bf61737649aa22a5dbc23107b89c
https://github.com/llvm/llvm-project/commit/27d2d8919133bf61737649aa22a5dbc23107b89c
Author: Simon Tatham <simon.tatham at arm.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M libc/config/baremetal/arm/entrypoints.txt
M libc/config/baremetal/riscv/entrypoints.txt
M libc/src/time/time_utils.h
Log Message:
-----------
[libc] Allow time conversions to compile on bare metal (#102014)
The `<time.h>` functions `asctime`, `gmtime`, `mktime` and their `_r`
variants are purely computational functions which convert between well
defined time representations and/or strings. There's no reason these
shouldn't be available in bare-metal builds of the library as well as
hosted ones: even if the library has no way to find out the time in
POSIX format, it might still see POSIX-style `time_t` values in input
data (e.g. network protocols) and need to interpret them.
The only obstacle to this was that the `out_of_range()` helper function
set `errno` to `EOVERFLOW`, which fails in a bare-metal build because
the extra POSIX error values aren't defined, including `EOVERFLOW`. So
I've made that assignment conditional on `EOVERFLOW` being defined.
Fixes #85556.
Commit: 92432b3c43b7ebb7e383d810cb4b519b9d08c6ed
https://github.com/llvm/llvm-project/commit/92432b3c43b7ebb7e383d810cb4b519b9d08c6ed
Author: Vladislav Khmelevsky <och95 at yandex.ru>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/include/llvm/ExecutionEngine/JITLink/aarch64.h
M llvm/lib/ExecutionEngine/JITLink/ELF_aarch64.cpp
M llvm/lib/ExecutionEngine/JITLink/MachO_arm64.cpp
M llvm/lib/ExecutionEngine/JITLink/aarch64.cpp
M llvm/test/ExecutionEngine/JITLink/AArch64/ELF_relocations.s
Log Message:
-----------
[JITLink][AArch64] Add LD64_GOTPAGE_LO15 rel support (#100854)
This relocation is used in order to address GOT entries using 15 bit
offset in ldr instruction. The offset is calculated relative to GOT
section page address.
Commit: 9979ba72ceb687ed4d1c7d0415c1d01ab5b0a7c6
https://github.com/llvm/llvm-project/commit/9979ba72ceb687ed4d1c7d0415c1d01ab5b0a7c6
Author: Nuno Lopes <nuno.lopes at tecnico.ulisboa.pt>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/test/DebugInfo/Generic/sroa-extract-bits.ll
M llvm/test/Transforms/InstCombine/dbg-scalable-store-fixed-frag.ll
M llvm/test/Transforms/InstCombine/debuginfo.ll
M llvm/test/Transforms/Mem2Reg/dbg_declare_to_value_conversions.ll
M llvm/test/Transforms/Mem2Reg/debug-alloca-vla-2.ll
Log Message:
-----------
[debuginfo] replace usage of undef with poison as placeholder [NFC]
Commit: 7b00d2109e1da2e093b9870501cc95c19436e3a7
https://github.com/llvm/llvm-project/commit/7b00d2109e1da2e093b9870501cc95c19436e3a7
Author: Ruiling, Song <ruiling.song at amd.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
A llvm/test/Transforms/StructurizeCFG/loop-break-phi.ll
Log Message:
-----------
[Tests] Copy while-break test to StructurizeCFG (#102118)
Copied from AMDGPU tests to show IR changes in later PR.
Commit: 2bd8bdcc2ce54a0ee78d91ef715973f94ab0adc5
https://github.com/llvm/llvm-project/commit/2bd8bdcc2ce54a0ee78d91ef715973f94ab0adc5
Author: Ricardo Jesus <rjj at nvidia.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/test/CodeGen/PowerPC/common-chain.ll
M llvm/test/Transforms/LICM/hoist-binop.ll
Log Message:
-----------
[LICM] Prevent fold and hoist of binary ops with over 2 uses (#102114)
This limits folding and hoisting associative binary ops to cases where
the intermediate op has at most two uses.
The more uses the intermediate op has, the more new ops we have to
create to potentially reduce the loop's critical path. We keep the limit
to two uses to minimise undesirable increases in code size.
Commit: d2926af5492b6df2fe09ef197f15392b33498369
https://github.com/llvm/llvm-project/commit/d2926af5492b6df2fe09ef197f15392b33498369
Author: Daniil Kovalev <dkovalev at accesssoftek.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
M llvm/lib/Target/AArch64/AArch64FastISel.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64MCInstLower.cpp
M llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp
M llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.h
A llvm/test/CodeGen/AArch64/ptrauth-basic-pic.ll
A llvm/test/CodeGen/AArch64/ptrauth-elf-globals-pic.ll
A llvm/test/CodeGen/AArch64/ptrauth-extern-weak.ll
A llvm/test/CodeGen/AArch64/ptrauth-got-abuse.ll
A llvm/test/CodeGen/AArch64/ptrauth-tagged-globals-pic.ll
A llvm/test/MC/AArch64/adrp-auth-relocation.s
M llvm/test/MC/AArch64/arm64-elf-relocs.s
M llvm/test/MC/AArch64/ilp32-diagnostics.s
Log Message:
-----------
[PAC][CodeGen][ELF][AArch64] Support signed GOT (#96164)
Depends on #96158 and #96159
Support the following relocations and assembly operators:
- `R_AARCH64_AUTH_ADR_GOT_PAGE` (`:got_auth:` for `adrp`)
- `R_AARCH64_AUTH_LD64_GOT_LO12_NC` (`:got_auth_lo12:` for `ldr`)
- `R_AARCH64_AUTH_GOT_ADD_LO12_NC` (`:got_auth_lo12:` for `add`)
`LOADgotAUTH` pseudo-instruction is introduced which is later expanded
to actual instruction sequence like the following.
```
adrp x16, :got_auth:sym
add x16, x16, :got_auth_lo12:sym
ldr x0, [x16]
autia x0, x16
```
If a resign is requested, like below, `LOADgotPAC` pseudo is used, and
GOT load is lowered similarly to `LOADgotAUTH`.
```
@var = global i32 0
define ptr @resign_globalvar() {
ret ptr ptrauth (ptr @var, i32 3, i64 43)
}
```
Both SelectionDAG and GlobalISel are suppported. For FastISel, we fall
back to SelectionDAG.
Tests starting with 'ptrauth-' have corresponding variants w/o this
prefix.
See also specification
https://github.com/ARM-software/abi-aa/blob/main/pauthabielf64/pauthabielf64.rst#appendix-signed-got
Commit: 765b8c258f556f3da048744b559f05d3a7efa1a7
https://github.com/llvm/llvm-project/commit/765b8c258f556f3da048744b559f05d3a7efa1a7
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M mlir/lib/Dialect/Vector/Transforms/LowerVectorContract.cpp
M mlir/test/Dialect/Vector/vector-contract-to-matrix-intrinsics-transforms.mlir
Log Message:
-----------
[nlir][vector] Constrain `ContractionOpToMatmulOpLowering` (#102225)
Disables `ContractionOpToMatmulOpLowering` for scalable vectors. This
pattern is meant to enable lowering to `llvm.matrix.multiply` - I'm not
aware of any use of that in the context of scalable vectors.
Commit: ed677398f7f9109a8cad103bc91484e784aac9ed
https://github.com/llvm/llvm-project/commit/ed677398f7f9109a8cad103bc91484e784aac9ed
Author: Oliver Stannard <oliver.stannard at arm.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M lld/ELF/Arch/ARM.cpp
M lld/ELF/Config.h
M lld/ELF/InputFiles.cpp
A lld/test/ELF/arm-mixed-plts.s
Log Message:
-----------
[lld][ARM] Fix assertion when mixing ARM and Thumb objects (#101985)
Previously, we selected the Thumb2 PLT sequences if any input object is
marked as not supporting the ARM ISA, which then causes assertion
failures when calls from ARM code in other objects are seen. I think the
intention here was to only use Thumb PLTs when the target does not have
the ARM ISA available, signalled by no objects being marked as having it
available. To do that we need to track which ISAs we have seen as we
parse the build attributes, and defer the decision about PLTs until all
input objects have been parsed.
This bug was triggered by real code in picolibc, which have some
versions of string.h functions built with Thumb2-only build attributes,
so that they are compatible with v7-A, v7-R and v7-M.
Fixes #99008.
Commit: bafb09543b37472600930e6a0c0a0f4584734d73
https://github.com/llvm/llvm-project/commit/bafb09543b37472600930e6a0c0a0f4584734d73
Author: Oliver Stannard <oliver.stannard at arm.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M clang/lib/Driver/ToolChain.cpp
M clang/test/Driver/fsanitize.c
Log Message:
-----------
[ARM] Enable cfi-icall for thumb triples (#102126)
Support for this was added back in 2016
(https://reviews.llvm.org/D27499), but never enabled in the driver.
Since then, it's been possible to enable this with an arm triple and the
-mthumb option, but not with a thumb triple.
This also caused -fsanitise=cfi to enable cfi-icall for arm triple but
not thumb triples, which caused spurious sanitiser failures if mixing
the two ISAs in one program.
Commit: a1a782b11a00fa1bbf454f5151b6f28a7444b02b
https://github.com/llvm/llvm-project/commit/a1a782b11a00fa1bbf454f5151b6f28a7444b02b
Author: Oliver Stannard <oliver.stannard at arm.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/lib/Target/ARM/ARMInstrThumb2.td
M llvm/test/CodeGen/ARM/setjmp-bti-basic.ll
Log Message:
-----------
[ARM] t2CALL_BTI pseudo-inst clobbers LR (#102117)
The t2CALL_BTI pseudo-instruction expands to a tBL instruction, so needs
the same implicit uses and defs as it.
Commit: a0d6c361818e7b0945f962c7fa82da12e877e23e
https://github.com/llvm/llvm-project/commit/a0d6c361818e7b0945f962c7fa82da12e877e23e
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/lib/Object/COFFObjectFile.cpp
Log Message:
-----------
Fix MSVC "not all control paths return a value" warning. NFC.
Commit: fab7cc4b480c9e961fbdeb2f07ae7466adde7d08
https://github.com/llvm/llvm-project/commit/fab7cc4b480c9e961fbdeb2f07ae7466adde7d08
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/lib/Object/COFFObjectFile.cpp
Log Message:
-----------
Remove unnecessary break to fix static analysis warning.
Commit: 71cbcbe1cdfd5df2220aaa6515d884b34935752c
https://github.com/llvm/llvm-project/commit/71cbcbe1cdfd5df2220aaa6515d884b34935752c
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/lib/Object/COFFObjectFile.cpp
Log Message:
-----------
Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFC.
Commit: 451ea65ffb96426f548195e11a30a9f463c1e0c1
https://github.com/llvm/llvm-project/commit/451ea65ffb96426f548195e11a30a9f463c1e0c1
Author: sinan <sinan.lin at linux.alibaba.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M bolt/lib/Rewrite/RewriteInstance.cpp
A bolt/test/AArch64/update-weak-reference-symbol.s
Log Message:
-----------
[BOLT] Skip PLT search for zero-value weak reference symbols (#69136)
Take a common weak reference pattern for example
```
__attribute__((weak)) void undef_weak_fun();
if (&undef_weak_fun)
undef_weak_fun();
```
In this case, an undefined weak symbol `undef_weak_fun` has an address
of zero, and Bolt incorrectly changes the relocation for the
corresponding symbol to symbol at PLT, leading to incorrect runtime
behavior.
Commit: 2ce3cd528a9eae0bcdb4c66a873212873fa9b7c8
https://github.com/llvm/llvm-project/commit/2ce3cd528a9eae0bcdb4c66a873212873fa9b7c8
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-fma.ll
Log Message:
-----------
AMDGPU/GlobalISel: Add test for fma_mix with source from unmerge (#102129)
When selecting fma_mix with operand that comes from G_UNMERGE_VALUES,
there is a bug where folded register is operand 0 of G_UNMERGE_VALUES.
Source modifiers are correctly selected.
isExtractHiElt returns G_UNMERGE_VALUES that defines source register
but does not specify which operand.
Commit: a544a32d095664463c4b0385739d394a27611df0
https://github.com/llvm/llvm-project/commit/a544a32d095664463c4b0385739d394a27611df0
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-fma.ll
Log Message:
-----------
AMDGPU/GlobalISel: Fix isExtractHiElt when selecting fma_mix (#102130)
isExtractHiElt should return new source register instead of returning
instruction that defines it. Src = MI.getOperand(0).getReg() is not
correct when MI(for example G_UNMERGE_VALUES) defines multiple registers.
Refactor existing code to work with source registers only.
Commit: 7c0de50f7c2bc7d4001190895883a69942985697
https://github.com/llvm/llvm-project/commit/7c0de50f7c2bc7d4001190895883a69942985697
Author: Vikram Hegde <115221833+vikramRH at users.noreply.github.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/Interp/State.h
M clang/test/AST/Interp/arrays.cpp
M clang/test/AST/Interp/builtin-functions.cpp
M clang/test/AST/Interp/vectors.cpp
M clang/test/CodeGenCXX/temporaries.cpp
A clang/test/SemaCXX/constexpr-vectors-access-elements.cpp
Log Message:
-----------
[clang][ExprConst] allow single element access of vector object to be constant expression (#101126)
This is a slightly updated version of https://github.com/llvm/llvm-project/pull/72607,
originally authored by @yuanfang-chen
Commit: 31c9ed003b6ddb1b724e3f15a3f274892956931c
https://github.com/llvm/llvm-project/commit/31c9ed003b6ddb1b724e3f15a3f274892956931c
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/lib/Analysis/BasicAliasAnalysis.cpp
A llvm/test/Analysis/BasicAA/nusw_nuw_nonneg.ll
Log Message:
-----------
[BasicAA] Make use of nusw+nuw -> nneg implication (#102141)
If the GEP is both nuw and inbounds/nusw, the offset is non-negative.
Pass this information to CastedValue and make use of it when determining
the value range.
Proof for nusw+nuw->nneg: https://alive2.llvm.org/ce/z/a_CKAw
Proof for the test case: https://alive2.llvm.org/ce/z/yJ3ymP
Commit: f113e291a35b8ba049a07daf6b5c59a3a3b62b4f
https://github.com/llvm/llvm-project/commit/f113e291a35b8ba049a07daf6b5c59a3a3b62b4f
Author: Paul Walker <paul.walker at arm.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/test/CodeGen/AArch64/sve-pred-selectop2.ll
M llvm/test/CodeGen/AArch64/sve-pred-selectop3.ll
Log Message:
-----------
[LLVM][ISel][SVE] Add patterns for merging reverse subtracts. (#101488)
vselect cond, ([f]sub b, a), a ==> [f]subr cond, a, b
Commit: 7d18294bd1becf8aee91cc5b4a19393460aa5a9a
https://github.com/llvm/llvm-project/commit/7d18294bd1becf8aee91cc5b4a19393460aa5a9a
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/reduced-value-replace-extractelement.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction-gather-non-scheduled-extracts.ll
Log Message:
-----------
[SLP]Fix PR102279: check the tracked values for extractelements, not the original values
If the reduced value was replaced by the extractelement instruction
during vectorization and we attempt to check if this is so, need to
check the tracked value, not the original (deleted) instruction.
Otherwise, the compiler may crash
Fixes https://github.com/llvm/llvm-project/issues/102279
Commit: fce9aefb2665a46482fcf28a6062ff5096b9faa2
https://github.com/llvm/llvm-project/commit/fce9aefb2665a46482fcf28a6062ff5096b9faa2
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M clang/lib/AST/Interp/Compiler.cpp
M clang/test/AST/Interp/vectors.cpp
Log Message:
-----------
[clang][Interp] Fix BooleanToSignedIntegral casts for IntAP(S) (#102302)
We were not doing the final Neg here.
Commit: 0d0adcd2e63daea5fd655e3b780e237453c5bfe0
https://github.com/llvm/llvm-project/commit/0d0adcd2e63daea5fd655e3b780e237453c5bfe0
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
M lldb/source/Plugins/SymbolFile/NativePDB/PdbAstBuilder.cpp
M lldb/source/Plugins/SymbolFile/NativePDB/UdtRecordCompleter.cpp
M lldb/source/Plugins/SymbolFile/PDB/PDBASTParser.cpp
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.h
M lldb/unittests/Symbol/TestTypeSystemClang.cpp
Log Message:
-----------
[lldb][TypeSystem] Pass ClangASTMetadata by-value when creating record/objc types (#102296)
This is a follow-up to https://github.com/llvm/llvm-project/pull/102161
where we changed the `GetMetadata`/`SetMetadata` APIs to pass
`ClangASTMetadata` by-value, instead of `ClangASTMetadata *`, which
wasn't a very friendly API.
This patch continues from there and changes
`CreateRecordType`/`CreateObjCClass` to take the metadata by-value as
well.
As a drive-by change, I also changed `DelayedAddObjCClassProperty` to
store the metadata by-value, instead of in a `std::unique_ptr`, which
AFAICT, was done solely due to the TypeSystemClang APIs taking the
metadata by pointer. This meant we could also get rid of the
user-provided copy constructors.
Commit: b4f06ed27b334396afcf29664d46aaea1c012dde
https://github.com/llvm/llvm-project/commit/b4f06ed27b334396afcf29664d46aaea1c012dde
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/tools/llvm-reduce/ReducerWorkItem.cpp
M llvm/tools/llvm-reduce/deltas/ReduceInstructionFlags.cpp
Log Message:
-----------
[llvm-reduce] Handle new flags in complexity score
This has gotten out of sync with the actual flag reduction. It's
not particularly important though, as it only seems to be used to
determine whether to do another round of delta reduction.
Commit: 5b966ffd4fd6fe264563700e5bfcf105a153a258
https://github.com/llvm/llvm-project/commit/5b966ffd4fd6fe264563700e5bfcf105a153a258
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEOps.td
M mlir/include/mlir/Dialect/ArmSME/Transforms/Passes.td
M mlir/lib/Dialect/ArmSME/Transforms/CMakeLists.txt
M mlir/lib/Dialect/ArmSME/Transforms/OuterProductFusion.cpp
M mlir/test/Dialect/ArmSME/outer-product-fusion.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/multi-tile-matmul-mixed-types.mlir
Log Message:
-----------
[mlir][ArmSME] Update `OuterProductFusion` to account for recent changes (#102125)
- Use vector.interleave rather than the LLVM intrinsic
- Remove dependency on LLVM dialect
- Remove manual outerproduct erases (these are now trivially dead)
- Remove comment explaining issues with previous tile allocator
- Update pipeline in `multi-tile-matmul-mixed-types.mlir`
Recent changes: #90448, #80965
Commit: f1c3dbcc1b82f5b442f269f40acb5104b3eca607
https://github.com/llvm/llvm-project/commit/f1c3dbcc1b82f5b442f269f40acb5104b3eca607
Author: Vladislav Khmelevsky <och95 at yandex.ru>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M bolt/lib/Rewrite/BinaryPassManager.cpp
Log Message:
-----------
[BOLT] Move ADRRelaxationPass (#101371)
For non-simple functions we need nop instruction to be presented to
transform ADR to ADRP+ADD sequence, so run this pass before remove nops
pass.
Commit: d6d48e8014875588c28a583300759f1728fdf2b4
https://github.com/llvm/llvm-project/commit/d6d48e8014875588c28a583300759f1728fdf2b4
Author: Vladislav Khmelevsky <och95 at yandex.ru>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M bolt/CMakeLists.txt
Log Message:
-----------
[BOLT][RUNTIME][NFC] Fix aarch64 match (#100866)
One of the problems related to #93151 is probably that aarch64 target
might have different names in different env, so extend aarch64 cmake cpu
match with different name aliases.
Commit: ad60a9e9b5ca3e94336173f0c1e9245e1ed7044e
https://github.com/llvm/llvm-project/commit/ad60a9e9b5ca3e94336173f0c1e9245e1ed7044e
Author: Vladislav Khmelevsky <och95 at yandex.ru>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M bolt/lib/Rewrite/RewriteInstance.cpp
A bolt/test/AArch64/Inputs/build_id.ldscript
A bolt/test/AArch64/build_id.c
A bolt/test/X86/Inputs/build_id.yaml
A bolt/test/X86/build_id.test
Log Message:
-----------
[BOLT] Fix relocations handling (#100890)
After porting BOLT to RISCV some of the relocations were broken on both
AArch64 and X86.
On AArch64 the example of broken relocations would be GOT, during
handling them, we should replace the symbol to __BOLT_got_zero in order
to address GOT entry, not the symbol that addresses this entry. This is
done further in code, so it is too early to add rel here.
On X86 it is a mistake to add relocations without addend. This is the
exact problem that is raised on #97937. Due to different code generation
I had to use gcc-generated yaml test, since with clang I wasn't able to
reproduce problem.
Added tests for both architectures and made the problematic condition
riscV-specific.
Commit: ac589ae4277d4643baa28e549fcd0049d73df136
https://github.com/llvm/llvm-project/commit/ac589ae4277d4643baa28e549fcd0049d73df136
Author: Vladislav Khmelevsky <och95 at yandex.ru>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M bolt/include/bolt/Core/BinaryContext.h
M bolt/lib/Core/BinaryContext.cpp
M bolt/lib/Rewrite/RewriteInstance.cpp
A bolt/test/AArch64/Inputs/got_end_of_section_symbol.lld_script
A bolt/test/AArch64/got_end_of_section_symbol.s
M bolt/test/X86/section-end-sym.s
Log Message:
-----------
[BOLT] Abort on out-of-section symbols in GOT (#100801)
This patch aborts BOLT execution if it finds out-of-section (section
end) symbol in GOT table. In order to handle such situations properly in
future, we would need to have an arch-dependent way to analyze
relocations or its sequences, e.g., for ARM it would probably be ADRP +
LDR analysis in order to get GOT entry address. Currently, it is also
challenging because GOT-related relocation symbols are replaced to
__BOLT_got_zero. Anyway, it seems to be quite a rare case, which seems
to be only? related to static binaries. For the most part, it seems that
it should be handled on the linker stage, since static binary should not
have GOT table at all. LLD linker with relaxations enabled would replace
instruction addresses from GOT directly to target symbols, which
eliminates the problem.
Anyway, in order to achieve detection of such cases, this patch fixes a
few things in BOLT:
1. For the end symbols, we're now using the section provided by ELF
binary. Previously it would be tied with a wrong section found by symbol
address.
2. The end symbols would have limited registration we would only
add them in name->data GlobalSymbols map, since using address->data
BinaryDataMap map would likely be impossible due to address duality of
such symbols.
3. The outdated BD->getSection (currently returning refence, not
pointer) check in postProcessSymbolTable is replaced by getSize check in
order to allow zero-sized top-level symbols if they are located in
zero-sized sections. For the most part, such things could only be found
in tests, but I don't see a reason not to handle such cases.
4. Updated section-end-sym test and removed x86_64 requirement since
there is no reason for this (tested on aarch64 linux)
The test was provided by peterwaller-arm (thank you) in #100096 and
slightly modified by me.
Commit: db5a6c09237caac1c5f5e8ec6ab3685aeb0f726e
https://github.com/llvm/llvm-project/commit/db5a6c09237caac1c5f5e8ec6ab3685aeb0f726e
Author: Job Henandez Lara <hj93 at protonmail.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/arm/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/math/index.rst
M libc/newhdrgen/yaml/math.yaml
M libc/spec/stdc.td
M libc/src/math/CMakeLists.txt
M libc/src/math/generic/CMakeLists.txt
A libc/src/math/generic/getpayloadl.cpp
A libc/src/math/getpayloadl.h
M libc/test/src/math/smoke/CMakeLists.txt
M libc/test/src/math/smoke/GetPayloadTest.h
A libc/test/src/math/smoke/getpayloadl_test.cpp
Log Message:
-----------
[libc][math] Add getpayloadl function. (#102214)
Commit: 6fdbb73787c3deb08b596095d3f2a259ba3a5606
https://github.com/llvm/llvm-project/commit/6fdbb73787c3deb08b596095d3f2a259ba3a5606
Author: Michael Maitland <michaeltmaitland at gmail.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M clang/test/Driver/riscv-cpus.c
M clang/test/Misc/target-invalid-cpu-note.c
M llvm/docs/ReleaseNotes.rst
M llvm/lib/Target/RISCV/RISCVProcessors.td
Log Message:
-----------
[RISCV] Add sifive-p470 processor (#102022)
This is an OOO core that has a vector unit. For more information see
https://www.sifive.com/cores/performance-p450-470.
Use the existing P400 scheduler model. This model is missing accurate
vector scheduling support, but it will be added in a follow up patch.
Other tunings can come in future patches too.
Commit: 89d3cf2d392e2eda1a9a54e75930744383e3be58
https://github.com/llvm/llvm-project/commit/89d3cf2d392e2eda1a9a54e75930744383e3be58
Author: Frank Schlimbach <frank.schlimbach at intel.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M mlir/include/mlir/Dialect/Mesh/IR/CMakeLists.txt
M mlir/include/mlir/Dialect/Mesh/IR/MeshBase.td
M mlir/include/mlir/Dialect/Mesh/IR/MeshOps.h
M mlir/include/mlir/Dialect/Mesh/IR/MeshOps.td
M mlir/include/mlir/Dialect/Mesh/Interfaces/ShardingInterface.h
M mlir/include/mlir/Dialect/Mesh/Interfaces/ShardingInterface.td
M mlir/include/mlir/Dialect/Mesh/Interfaces/ShardingInterfaceImpl.h
A mlir/include/mlir/Dialect/Tensor/IR/ShardingInterfaceImpl.h
M mlir/include/mlir/InitAllDialects.h
M mlir/include/mlir/Interfaces/InferTypeOpInterface.h
M mlir/lib/Dialect/Linalg/Transforms/MeshShardingInterfaceImpl.cpp
M mlir/lib/Dialect/Mesh/IR/MeshOps.cpp
M mlir/lib/Dialect/Mesh/Interfaces/ShardingInterface.cpp
M mlir/lib/Dialect/Mesh/Transforms/ShardingPropagation.cpp
M mlir/lib/Dialect/Mesh/Transforms/Spmdization.cpp
M mlir/lib/Dialect/Tensor/IR/CMakeLists.txt
A mlir/lib/Dialect/Tensor/IR/ShardingInterfaceImpl.cpp
M mlir/test/Dialect/Linalg/mesh-sharding-propagation.mlir
M mlir/test/Dialect/Linalg/mesh-spmdization.mlir
M mlir/test/Dialect/Mesh/canonicalization.mlir
M mlir/test/Dialect/Mesh/invalid.mlir
M mlir/test/Dialect/Mesh/ops.mlir
M mlir/test/Dialect/Mesh/resharding-spmdization.mlir
M mlir/test/Dialect/Mesh/sharding-propagation.mlir
M mlir/test/Dialect/Mesh/simplifications.mlir
M mlir/test/Dialect/Mesh/spmdization.mlir
A mlir/test/Dialect/Tensor/mesh-spmdization.mlir
M mlir/test/lib/Dialect/Mesh/TestReshardingSpmdization.cpp
Log Message:
-----------
[mlir][mesh] adding shard-size control (#98145)
- Replacing `#mesh.sharding` attribute with operation `mesh.sharding`
- extended semantics now allow providing optional `halo_sizes` and
`sharded_dims_sizes`
- internally a sharding is represented as a non-IR class
`mesh::MeshSharding`
What previously was
```mlir
%sharded0 = mesh.shard %arg0 <@mesh0, [[0]]> : tensor<4x8xf32>
%sharded1 = mesh.shard %arg1 <@mesh0, [[0]]> annotate_for_users : tensor<16x8xf32>
```
is now
```mlir
%sharding = mesh.sharding @mesh0, [[0]] : !mesh.sharding
%0 = mesh.shard %arg0 to %sharding : tensor<4x8xf32>
%1 = mesh.shard %arg1 to %sharding annotate_for_users : tensor<16x8xf32>
```
and allows additional annotations to control the shard sizes:
```mlir
mesh.mesh @mesh0 (shape = 4)
%sharding0 = mesh.sharding @mesh0, [[0]] halo_sizes = [1, 2] : !mesh.sharding
%0 = mesh.shard %arg0 to %sharding0 : tensor<4x8xf32>
%sharding1 = mesh.sharding @mesh0, [[0]] sharded_dims_sizes = [3, 5, 5, 3] : !mesh.sharding
%1 = mesh.shard %arg1 to %sharding1 annotate_for_users : tensor<16x8xf32>
```
- `mesh.shard` op accepts additional optional attribute `force`, useful
for halo updates
- Some initial spmdization support for the new semantics
- Support for `tensor.empty` reacting on `sharded_dims_sizes` and
`halo_sizes` in the sharding
- New collective operation `mesh.update_halo` as a spmdized target for
shardings with `halo_sizes`
@sogartar @yaochengji
Commit: de422e21b861e856fe339553bd8ac2413a8022eb
https://github.com/llvm/llvm-project/commit/de422e21b861e856fe339553bd8ac2413a8022eb
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
Log Message:
-----------
[lldb][ClangExpressionParser][NFC] Remove unused local vars
These got removed in `d6cbcf93b227befaad00957a56acd63c837c26ff` but
mistakenly added back when rebasing `12e3a06cb7615fbd91031420f3dec2a85d7877d6`
Commit: 9a40a3ccd5ab0fcb49f7caa79fcf8b240f02e963
https://github.com/llvm/llvm-project/commit/9a40a3ccd5ab0fcb49f7caa79fcf8b240f02e963
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/test/TableGen/SubtargetFeatureUniqueNames.td
Log Message:
-----------
[NFC] Temporarily disable failing TableGen unit test. (#102308)
- This test was reported as failing in ASAN builds, with
non-deterministic order of the error message and note expected.
- This is due to llvm::sort() being unstable.
- Temporarily disable the test while its been fixed.
Commit: 5138e767ba8a9407c950dfd4abbdc4cc5db3aa48
https://github.com/llvm/llvm-project/commit/5138e767ba8a9407c950dfd4abbdc4cc5db3aa48
Author: Chinmay Deshpande <cddeshpa at uci.edu>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/include/llvm/MCA/Stages/InOrderIssueStage.h
M llvm/lib/MCA/Stages/InOrderIssueStage.cpp
Log Message:
-----------
`InOrderIssueStage` for llvm-mca should be generic over LSUnitBase (#101534)
Other HardwareUnits (such as the
[Scheduler](https://github.com/llvm/llvm-project/blob/main/llvm/include/llvm/MCA/HardwareUnits/Scheduler.h#L71))
and Stages (such as
[RetireStage](https://github.com/llvm/llvm-project/blob/main/llvm/include/llvm/MCA/Stages/RetireStage.h#L32))
are generic over `LSUnitBase` rather than the specialized `LSUnit`.
Commit: 573a48489f9532fb1e7276497459cf19972837ce
https://github.com/llvm/llvm-project/commit/573a48489f9532fb1e7276497459cf19972837ce
Author: Abhina Sree <Abhina.Sreeskantharajan at ibm.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M clang/lib/Basic/IdentifierTable.cpp
Log Message:
-----------
[NFC] Format TokenKey enum (#101700)
This is to fix the white-space formatting of the TokenKey enum
Commit: e41b907e1c989c64886a306102334d40d2da25c9
https://github.com/llvm/llvm-project/commit/e41b907e1c989c64886a306102334d40d2da25c9
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M libc/include/llvm-libc-macros/limits-macros.h
Log Message:
-----------
[libc] Define `MB_LEN_MAX` in `limits.h` (#102246)
Summary:
This is supposed to define the maximum bytes required to store a char in
any locale. There's some question about what this should be set to. I
believe because the proposed solution for `locale.h` is to only support
the default locale, we should do what `musl` does and set it to `4`
which covers up to UTF-32.
Fixes https://github.com/llvm/llvm-project/issues/79358
Commit: b95e9d08484c21840933b31b6fab1b280d3edc67
https://github.com/llvm/llvm-project/commit/b95e9d08484c21840933b31b6fab1b280d3edc67
Author: Michael Maitland <michaeltmaitland at gmail.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/include/llvm/CodeGen/SDPatternMatch.h
Log Message:
-----------
[DAG][NFC] Remove unnecessary default arguments (#100737)
Commit: 5c2e8d9ff2981285b2b6360500c4e6af8f55e833
https://github.com/llvm/llvm-project/commit/5c2e8d9ff2981285b2b6360500c4e6af8f55e833
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M libc/include/llvm-libc-macros/float-macros.h
Log Message:
-----------
[libc] Add `*_HAS_SUBNORM` to `float.h` (#102182)
Summary:
These should be defined, since we provide `float.h` it will override the
Clang resource dir and not provide it.
Commit: 2d87dc744addf313d61608efb13237ced10bd853
https://github.com/llvm/llvm-project/commit/2d87dc744addf313d61608efb13237ced10bd853
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M libc/config/gpu/entrypoints.txt
Log Message:
-----------
[libc] Enable quick_exit routines on the GPU (#102242)
Summary:
We should be able to use these on the GPU just like exit.
Commit: 14026f4d724ffa085b1a65047fef84ef70979a1e
https://github.com/llvm/llvm-project/commit/14026f4d724ffa085b1a65047fef84ef70979a1e
Author: Zibi Sarbinowski <zibi at ca.ibm.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M libcxx/test/std/numerics/c.math/hermite.pass.cpp
Log Message:
-----------
[libcxx][test][z/OS] Fix hermite.pass.cpp for HEX float (#101019)
The HEX float on z/OS does not have infinity nor NaN. In addition, the
limits are smaller before the overflow occurs in mathematical
calculations. This PR accounts for this.
FYI, this LIT test was recently added in PR
[89982](https://github.com/llvm/llvm-project/pull/89982)
Commit: 0caba9ab67a1c8a710fd6b65de10c61e59735e7f
https://github.com/llvm/llvm-project/commit/0caba9ab67a1c8a710fd6b65de10c61e59735e7f
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/include/llvm/Transforms/IPO/Attributor.h
M llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
M llvm/lib/Transforms/IPO/Attributor.cpp
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
M llvm/test/CodeGen/AMDGPU/direct-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/duplicate-attribute-indirect.ll
R llvm/test/CodeGen/AMDGPU/simple-indirect-call-2.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
Log Message:
-----------
Revert "Reapply "[Attributor][AMDGPU] Enable AAIndirectCallInfo for AMDAttributor (#100952)""
This reverts commit 7a68449a82ab1c1ab005caa72c1d986ca5deca36.
https://lab.llvm.org/buildbot/#/builders/123/builds/3205
Commit: 3287e7ed47de20a59d325b0d0dc27b12897535b8
https://github.com/llvm/llvm-project/commit/3287e7ed47de20a59d325b0d0dc27b12897535b8
Author: Donát Nagy <donat.nagy at ericsson.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/CoreEngine.h
Log Message:
-----------
[analyzer][NFC] Prune a very obsolete comment about CoreEngine (#101173)
Once upon a time, a long time (16 years) ago there were two classes
called `GREngineImpl` and `template <class CHECKER> GrEngine`. As the
years passed, they were merged into a single class that went through
several renames, but this comment still preserved the memory of their
old relationship... until now.
Commit: da1d2634843c57808722acd84679a6b22df7ce8c
https://github.com/llvm/llvm-project/commit/da1d2634843c57808722acd84679a6b22df7ce8c
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M mlir/lib/Dialect/Mesh/IR/MeshOps.cpp
Log Message:
-----------
[mlir] Fix -Wunused-variable in MeshOps.cpp (NFC)
/llvm-project/mlir/lib/Dialect/Mesh/IR/MeshOps.cpp:182:16:
error: unused variable 'inAxis' [-Werror,-Wunused-variable]
auto inAxis = dimSz % inShape.size();
^
Commit: 8e7cd50319caebda62bb5f7053744465b7f5dd18
https://github.com/llvm/llvm-project/commit/8e7cd50319caebda62bb5f7053744465b7f5dd18
Author: OverMighty <its.overmighty at gmail.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/math/index.rst
M libc/spec/stdc.td
M libc/src/math/CMakeLists.txt
A libc/src/math/exp10f16.h
M libc/src/math/generic/CMakeLists.txt
A libc/src/math/generic/exp10f16.cpp
M libc/src/math/generic/exp2f16.cpp
A libc/src/math/generic/expxf16.h
M libc/test/src/math/CMakeLists.txt
A libc/test/src/math/exp10f16_test.cpp
M libc/test/src/math/performance_testing/CMakeLists.txt
A libc/test/src/math/performance_testing/exp10f16_perf.cpp
M libc/test/src/math/smoke/CMakeLists.txt
A libc/test/src/math/smoke/exp10f16_test.cpp
Log Message:
-----------
[libc][math][c23] Add exp10f16 C23 math function (#101588)
Part of #95250.
Commit: 953d1f15991b5a49e232375b7dedb7bc60f72b6e
https://github.com/llvm/llvm-project/commit/953d1f15991b5a49e232375b7dedb7bc60f72b6e
Author: Zaara Syeda <syzaara at ca.ibm.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
M llvm/test/CodeGen/PowerPC/aix-base-pointer.ll
Log Message:
-----------
[PPC][AIX] Save/restore r31 when using base pointer (#100182)
When the base pointer r30 is used to hold the stack pointer, r30 is
spilled in the prologue. On AIX registers are saved from highest to
lowest, so r31 also needs to be saved.
Fixes https://github.com/llvm/llvm-project/issues/96411
Commit: 77a3750d12ca0dfb0464153b67255038b29e98ba
https://github.com/llvm/llvm-project/commit/77a3750d12ca0dfb0464153b67255038b29e98ba
Author: Renato Golin <rengolin at systemcall.eu>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M mlir/include/mlir/Dialect/Mesh/IR/CMakeLists.txt
M mlir/include/mlir/Dialect/Mesh/IR/MeshBase.td
M mlir/include/mlir/Dialect/Mesh/IR/MeshOps.h
M mlir/include/mlir/Dialect/Mesh/IR/MeshOps.td
M mlir/include/mlir/Dialect/Mesh/Interfaces/ShardingInterface.h
M mlir/include/mlir/Dialect/Mesh/Interfaces/ShardingInterface.td
M mlir/include/mlir/Dialect/Mesh/Interfaces/ShardingInterfaceImpl.h
R mlir/include/mlir/Dialect/Tensor/IR/ShardingInterfaceImpl.h
M mlir/include/mlir/InitAllDialects.h
M mlir/include/mlir/Interfaces/InferTypeOpInterface.h
M mlir/lib/Dialect/Linalg/Transforms/MeshShardingInterfaceImpl.cpp
M mlir/lib/Dialect/Mesh/IR/MeshOps.cpp
M mlir/lib/Dialect/Mesh/Interfaces/ShardingInterface.cpp
M mlir/lib/Dialect/Mesh/Transforms/ShardingPropagation.cpp
M mlir/lib/Dialect/Mesh/Transforms/Spmdization.cpp
M mlir/lib/Dialect/Tensor/IR/CMakeLists.txt
R mlir/lib/Dialect/Tensor/IR/ShardingInterfaceImpl.cpp
M mlir/test/Dialect/Linalg/mesh-sharding-propagation.mlir
M mlir/test/Dialect/Linalg/mesh-spmdization.mlir
M mlir/test/Dialect/Mesh/canonicalization.mlir
M mlir/test/Dialect/Mesh/invalid.mlir
M mlir/test/Dialect/Mesh/ops.mlir
M mlir/test/Dialect/Mesh/resharding-spmdization.mlir
M mlir/test/Dialect/Mesh/sharding-propagation.mlir
M mlir/test/Dialect/Mesh/simplifications.mlir
M mlir/test/Dialect/Mesh/spmdization.mlir
R mlir/test/Dialect/Tensor/mesh-spmdization.mlir
M mlir/test/lib/Dialect/Mesh/TestReshardingSpmdization.cpp
Log Message:
-----------
Revert "[mlir][mesh] adding shard-size control (#98145)"
This reverts commit fca69838caf19854769ada21a71da91fcfcbde73.
Also reverts the fixup: "[mlir] Fix -Wunused-variable in MeshOps.cpp (NFC)"
This reverts commit fc737368fe6e27d6ecf76e522cb43a32aaca992a.
Commit: 8654e48fa69245ed54a6df1b7d70f8f805a16fbe
https://github.com/llvm/llvm-project/commit/8654e48fa69245ed54a6df1b7d70f8f805a16fbe
Author: Lucas Duarte Prates <lucas.prates at arm.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
A llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-exchange-fence.ll
Log Message:
-----------
[AArch64] Don't replace dst of SWP instructions with (X|W)ZR (#102139)
This change updates the AArch64DeadRegisterDefinition pass to ensure it
does not replace the destination register of a SWP instruction with the
zero register when its value is unused. This is necessary to ensure that
the ordering of such instructions in relation to DMB.LD barries adheres
to the definitions of the AArch64 Memory Model.
The memory model states the following (ARMARM version DDI 0487K.a
§B2.3.7):
```
Barrier-ordered-before
An effect E1 is Barrier-ordered-before an effect E2 if one of the following applies:
[...]
* All of the following apply:
- E1 is a Memory Read effect.
- E1 is generated by an instruction whose destination register is not WZR or XZR.
- E1 appears in program order before E3.
- E3 is either a DMB LD effect or a DSB LD effect.
- E3 appears in program order before E2.
```
Prior to this change, by replacing the destination register of such SWP
instruction with WZR/XZR, the ordering relation described above was
incorrectly removed from the generated code.
The new behaviour is ensured in this patch by adding the relevant
`SWP[L](B|H|W|X)` instructions to list in the `atomicReadDroppedOnZero`
predicate, which already covered the `LD<Op>` instructions that are
subject to the same effect.
Fixes #68428.
Commit: 31461c3daa04d96cc20f023ecfd6a2cfa75b3bca
https://github.com/llvm/llvm-project/commit/31461c3daa04d96cc20f023ecfd6a2cfa75b3bca
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M libc/utils/gpu/server/CMakeLists.txt
Log Message:
-----------
[libc] Fix bot accidentally picking up conflicting MB_LEN_MAX
Commit: 18fae030c14c54987316765e10bdd2487a27bb66
https://github.com/llvm/llvm-project/commit/18fae030c14c54987316765e10bdd2487a27bb66
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/test/Transforms/InstSimplify/insertelement.ll
Log Message:
-----------
[InstSimplify] Fold (insertelement Splat(C), C, X) -> Splat(C) (#102315)
The index doesn't matter here.
Commit: f39fad48024aef70fd6753c31912efe2ccc326ee
https://github.com/llvm/llvm-project/commit/f39fad48024aef70fd6753c31912efe2ccc326ee
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/test/Transforms/SimplifyCFG/X86/sink-common-code.ll
Log Message:
-----------
[SimplifyCFG] Add tests for sinking of load/store + gep (NFC)
Commit: 921d9d370764b76e20afa5efd3f79e482de17386
https://github.com/llvm/llvm-project/commit/921d9d370764b76e20afa5efd3f79e482de17386
Author: Pradeep Kumar <pradeepku at nvidia.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/docs/NVPTXUsage.rst
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
A llvm/test/CodeGen/NVPTX/fence-proxy-tensormap.ll
Log Message:
-----------
[LLVM][NVPTX] Add NVPTX codegen support for fence.proxy.tensormap (#100748)
This commit adds LLVM Intrinsics and NVPTX codegen support for
`fence.proxy.tensormap` with lit tests under fence-proxy-tensormap.ll.
Also, added Intrinsics documentation in NVPTXUsage.rst
---------
Co-authored-by: gonzalobg <65027571+gonzalobg at users.noreply.github.com>
Commit: 5f96be7fa79cff24dc7f15e4f2495ddf7ca20346
https://github.com/llvm/llvm-project/commit/5f96be7fa79cff24dc7f15e4f2495ddf7ca20346
Author: royitaqi <royitaqi at users.noreply.github.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M lldb/source/Core/Progress.cpp
M lldb/unittests/Core/ProgressReportTest.cpp
Log Message:
-----------
[lldb] Make sure that a `Progress` "completed" update is always reported at destruction (#102097)
Make all `Progress` destructions to cause `progressEnd` events,
regardless of the value of `m_completed` before the destruction.
Currently, a `Progress` instance with `m_completed != 0 && m_complete !=
m_total` will cause a `progressUpdate` event (not `progressEnd`) at
destruction and. This contradicts with the classdoc: "a progress completed
update is reported even if the user doesn't explicitly cause one to be sent."
Commit: 2de620a9b7c68d84dd9750b5ba7617c96e9dd01c
https://github.com/llvm/llvm-project/commit/2de620a9b7c68d84dd9750b5ba7617c96e9dd01c
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M flang/lib/Lower/DirectivesCommon.h
M flang/lib/Lower/OpenACC.cpp
M flang/test/Lower/OpenACC/acc-bounds.f90
Log Message:
-----------
[flang][acc] Improve lowering of Fortran optional in data clause (#102224)
Fortran optional arguments are effectively null references. To deal with
this possibility, flang lowering of OpenACC data clauses creates three
if-else regions when preparing the data pointer for the data clause:
1) Load box value from box reference
2) Load box addr from box value
3) Load box dims from box value
However, this pattern makes it more complicated to find the original box
reference. Effectively, the first if-else region to get the box value is
not needed - since the value can be loaded before the corresponding
`fir.box_addr` and `fir.box_dims` operations. Thus, reduce the number of
if-else regions by deferring the box load to the use sites.
For non-optional cases, the old functionality is left alone - which
preloads the box value.
Commit: 34bf2fc8cbc34aa6ffa41d4f226c0e7d6249f345
https://github.com/llvm/llvm-project/commit/34bf2fc8cbc34aa6ffa41d4f226c0e7d6249f345
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M libc/utils/gpu/server/rpc_server.cpp
Log Message:
-----------
[libc] Fix conflict values from internal `limits.h` when used externally
Commit: b3baf31225aed40ae1a2f5e214abb299aa9b0b7d
https://github.com/llvm/llvm-project/commit/b3baf31225aed40ae1a2f5e214abb299aa9b0b7d
Author: Nhat Nguyen <hoangnhat2911 at gmail.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M mlir/python/requirements.txt
Log Message:
-----------
[mlir] [python] Update PyYAML minimum version to 5.4 and limit ml_dtypes to 0.4.0 (#102178)
PyYAML 5.3.1 has a security vulnerability as described here:
https://nvd.nist.gov/vuln/detail/CVE-2020-14343. Update the minimum
PyYAML version to 5.4. Also limit ml_dtypes version to 0.4.0.
Commit: 3e42aa4fab2f68bef904b89820ce49d6d2171ab1
https://github.com/llvm/llvm-project/commit/3e42aa4fab2f68bef904b89820ce49d6d2171ab1
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp
Log Message:
-----------
Fix gcc Wparentheses warning. NFC.
Commit: 911803308a1c22320f09167b5fb57d9d6c82cef1
https://github.com/llvm/llvm-project/commit/911803308a1c22320f09167b5fb57d9d6c82cef1
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
Log Message:
-----------
Fix gcc Wparentheses warning. NFC.
Commit: c67fa64a5eb53dd4e629c3e486a1a3a7b4447af8
https://github.com/llvm/llvm-project/commit/c67fa64a5eb53dd4e629c3e486a1a3a7b4447af8
Author: Mital Ashok <mital at mitalashok.co.uk>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
Log Message:
-----------
[Clang][NFC] Restore "Non-comprehensive list of changes in this release" in ReleaseNotes (#102134)
This was removed in 10c6d6349e51bb245b9deec4aafca9885971135b
Commit: 96e86bc9055909f220a050fca286540e8cc9d00b
https://github.com/llvm/llvm-project/commit/96e86bc9055909f220a050fca286540e8cc9d00b
Author: Han-Kuan Chen <hankuan.chen at sifive.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/revec.ll
Log Message:
-----------
[SLP][REVEC] Make ShuffleCostEstimator and ShuffleInstructionBuilder support vector instructions. (#99499)
1. When REVEC is enabled, we need to expand vector types into scalar
types.
2. When REVEC is enabled, CreateInsertVector (and CreateExtractVector)
is used because the scalar type may be a FixedVectorType.
3. Since the mask indices which are used by processBuildVector expect
the source is scalar type, we need to transform the mask indices into a
form which can be used when REVEC is enabled. The transform is only
called when the mask is really used.
Commit: 01925ee39c6bcbe70e7a2b5baa0735833f2ca5b4
https://github.com/llvm/llvm-project/commit/01925ee39c6bcbe70e7a2b5baa0735833f2ca5b4
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/test/CodeGen/AArch64/abds-neg.ll
M llvm/test/CodeGen/AArch64/abds.ll
M llvm/test/CodeGen/AArch64/abdu-neg.ll
M llvm/test/CodeGen/AArch64/abdu.ll
M llvm/test/CodeGen/AArch64/arm64-vabs.ll
M llvm/test/CodeGen/AArch64/neon-abd.ll
M llvm/test/CodeGen/AArch64/sve-aba.ll
M llvm/test/CodeGen/AArch64/sve-abd.ll
M llvm/test/CodeGen/AMDGPU/sad.ll
M llvm/test/CodeGen/ARM/neon_vabd.ll
M llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll
M llvm/test/CodeGen/PowerPC/vec-zext-abdu.ll
M llvm/test/CodeGen/RISCV/abds-neg.ll
M llvm/test/CodeGen/RISCV/abds.ll
M llvm/test/CodeGen/RISCV/abdu-neg.ll
M llvm/test/CodeGen/RISCV/abdu.ll
M llvm/test/CodeGen/RISCV/rvv/abd.ll
M llvm/test/CodeGen/Thumb2/mve-vabdus.ll
M llvm/test/CodeGen/X86/abds-neg.ll
M llvm/test/CodeGen/X86/abds.ll
M llvm/test/CodeGen/X86/abdu-neg.ll
M llvm/test/CodeGen/X86/abdu.ll
Log Message:
-----------
Revert b1234ddbe2652aa7948242a57107ca7ab12fd2f8. "[DAG] Add legalization handling for ABDS/ABDU (#92576)"
Reverting #92576 while we identify a reported regression
Commit: bb24f0d32235b778b94140166f2bc3452102adfe
https://github.com/llvm/llvm-project/commit/bb24f0d32235b778b94140166f2bc3452102adfe
Author: Steven Wu <stevenwu at apple.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M clang-tools-extra/clang-tidy/tool/CMakeLists.txt
M clang/cmake/modules/AddClang.cmake
M clang/tools/clang-linker-wrapper/CMakeLists.txt
M clang/tools/clang-repl/CMakeLists.txt
M clang/tools/driver/CMakeLists.txt
M clang/unittests/Interpreter/CMakeLists.txt
M clang/unittests/Interpreter/ExceptionTests/CMakeLists.txt
M flang/tools/flang-driver/CMakeLists.txt
M lld/cmake/modules/AddLLD.cmake
M lld/tools/lld/CMakeLists.txt
M llvm/CMakeLists.txt
M llvm/cmake/modules/AddLLVM.cmake
M llvm/examples/ExceptionDemo/CMakeLists.txt
M llvm/examples/HowToUseLLJIT/CMakeLists.txt
M llvm/examples/Kaleidoscope/BuildingAJIT/Chapter1/CMakeLists.txt
M llvm/examples/Kaleidoscope/BuildingAJIT/Chapter2/CMakeLists.txt
M llvm/examples/Kaleidoscope/BuildingAJIT/Chapter3/CMakeLists.txt
M llvm/examples/Kaleidoscope/BuildingAJIT/Chapter4/CMakeLists.txt
M llvm/examples/Kaleidoscope/CMakeLists.txt
M llvm/examples/Kaleidoscope/Chapter4/CMakeLists.txt
M llvm/examples/Kaleidoscope/Chapter5/CMakeLists.txt
M llvm/examples/Kaleidoscope/Chapter6/CMakeLists.txt
M llvm/examples/Kaleidoscope/Chapter7/CMakeLists.txt
M llvm/examples/Kaleidoscope/Chapter8/CMakeLists.txt
M llvm/examples/Kaleidoscope/Chapter9/CMakeLists.txt
M llvm/examples/OrcV2Examples/LLJITDumpObjects/CMakeLists.txt
M llvm/examples/OrcV2Examples/LLJITRemovableCode/CMakeLists.txt
M llvm/examples/OrcV2Examples/LLJITWithCustomObjectLinkingLayer/CMakeLists.txt
M llvm/examples/OrcV2Examples/LLJITWithExecutorProcessControl/CMakeLists.txt
M llvm/examples/OrcV2Examples/LLJITWithGDBRegistrationListener/CMakeLists.txt
M llvm/examples/OrcV2Examples/LLJITWithInitializers/CMakeLists.txt
M llvm/examples/OrcV2Examples/LLJITWithLazyReexports/CMakeLists.txt
M llvm/examples/OrcV2Examples/LLJITWithObjectCache/CMakeLists.txt
M llvm/examples/OrcV2Examples/LLJITWithObjectLinkingLayerPlugin/CMakeLists.txt
M llvm/examples/OrcV2Examples/LLJITWithOptimizingIRTransform/CMakeLists.txt
M llvm/examples/OrcV2Examples/LLJITWithRemoteDebugging/CMakeLists.txt
M llvm/examples/OrcV2Examples/LLJITWithThinLTOSummaries/CMakeLists.txt
M llvm/examples/OrcV2Examples/OrcV2CBindingsAddObjectFile/CMakeLists.txt
M llvm/examples/OrcV2Examples/OrcV2CBindingsBasicUsage/CMakeLists.txt
M llvm/examples/OrcV2Examples/OrcV2CBindingsDumpObjects/CMakeLists.txt
M llvm/examples/OrcV2Examples/OrcV2CBindingsIRTransforms/CMakeLists.txt
M llvm/examples/OrcV2Examples/OrcV2CBindingsLazy/CMakeLists.txt
M llvm/examples/OrcV2Examples/OrcV2CBindingsRemovableCode/CMakeLists.txt
M llvm/examples/OrcV2Examples/OrcV2CBindingsVeryLazy/CMakeLists.txt
M llvm/tools/bugpoint/CMakeLists.txt
M llvm/tools/llc/CMakeLists.txt
M llvm/tools/lli/CMakeLists.txt
M llvm/tools/lli/ChildTarget/CMakeLists.txt
M llvm/tools/llvm-jitlink/CMakeLists.txt
M llvm/tools/llvm-jitlink/llvm-jitlink-executor/CMakeLists.txt
M llvm/tools/llvm-lto2/CMakeLists.txt
M llvm/tools/opt/CMakeLists.txt
M llvm/unittests/Analysis/CMakeLists.txt
M llvm/unittests/ExecutionEngine/Orc/CMakeLists.txt
M llvm/unittests/Passes/Plugins/CMakeLists.txt
M llvm/unittests/Support/DynamicLibrary/CMakeLists.txt
M mlir/tools/mlir-cpu-runner/CMakeLists.txt
M mlir/tools/mlir-opt/CMakeLists.txt
Log Message:
-----------
Reapply "[CMake] Fold export_executable_symbols_* into function args. (#101741)" (#102138)
Fix the builds with LLVM_TOOL_LLVM_DRIVER_BUILD enabled.
LLVM_ENABLE_EXPORTED_SYMBOLS_IN_EXECUTABLES is not completely
compatible with export_executable_symbols as the later will be ignored
if the previous is set to NO.
Fix the issue by passing if symbols need to be exported to
llvm_add_exectuable so the link flag can be determined directly
without calling export_executable_symbols_* later.
Commit: 322a521a0f1cdc067489de08f69809e7f2e088c2
https://github.com/llvm/llvm-project/commit/322a521a0f1cdc067489de08f69809e7f2e088c2
Author: John McIver <john.mciver.iii at gmail.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/test/Transforms/SLPVectorizer/X86/addsub.ll
M llvm/test/Transforms/SLPVectorizer/X86/fmuladd.ll
Log Message:
-----------
[SLP][NFC] Add freeze instruction tests for upcoming support (#102215)
Commit: 8b347d87f8871599f0c5ccabe424880b75ae1a84
https://github.com/llvm/llvm-project/commit/8b347d87f8871599f0c5ccabe424880b75ae1a84
Author: SpencerAbson <Spencer.Abson at arm.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M clang/include/clang/Basic/arm_sve.td
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_clamp.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_max.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_maxnm.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_min.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_minnm.c
M clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_bfadd.c
M clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_bfclamp.c
M clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_bfmax.c
M clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c
M clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_bfmin.c
M clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_bfminnm.c
M clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_bfmla.c
M clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c
M clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_bfmls.c
M clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c
M clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_bfmul.c
M clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c
M clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_bfsub.c
M clang/test/Driver/print-supported-extensions-aarch64.c
M clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_b16b16.cpp
A clang/test/Sema/aarch64-sve2p1-intrinsics/acle_sve2p1_b16b16.cpp
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/test/CodeGen/AArch64/sme2-intrinsics-max.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-min.ll
M llvm/test/CodeGen/AArch64/sve2-min-max-clamp.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfadd.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfclamp.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfmax.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfmaxnm.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfmin.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfminnm.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfmla.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfmla_lane.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfmls.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfmls_lane.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfmul.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfmul_lane.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfsub.ll
M llvm/test/MC/AArch64/SME2/bfclamp-diagnostics.s
M llvm/test/MC/AArch64/SME2/bfclamp.s
M llvm/test/MC/AArch64/SME2/bfmax-diagnostics.s
M llvm/test/MC/AArch64/SME2/bfmax.s
M llvm/test/MC/AArch64/SME2/bfmaxnm-diagnostics.s
M llvm/test/MC/AArch64/SME2/bfmaxnm.s
M llvm/test/MC/AArch64/SME2/bfmin-diagnostics.s
M llvm/test/MC/AArch64/SME2/bfmin.s
M llvm/test/MC/AArch64/SME2/bfminnm-diagnostics.s
M llvm/test/MC/AArch64/SME2/bfminnm.s
M llvm/test/MC/AArch64/SME2p1/directive-arch-negative.s
M llvm/test/MC/AArch64/SME2p1/directive-arch.s
M llvm/test/MC/AArch64/SME2p1/directive-arch_extension-negative.s
M llvm/test/MC/AArch64/SME2p1/directive-arch_extension.s
M llvm/test/MC/AArch64/SVE2p1/bfadd-diagnostics.s
M llvm/test/MC/AArch64/SVE2p1/bfadd.s
M llvm/test/MC/AArch64/SVE2p1/bfclamp-diagnostics.s
M llvm/test/MC/AArch64/SVE2p1/bfclamp.s
M llvm/test/MC/AArch64/SVE2p1/bfmax-diagnostics.s
M llvm/test/MC/AArch64/SVE2p1/bfmax.s
M llvm/test/MC/AArch64/SVE2p1/bfmaxnm-diagnostics.s
M llvm/test/MC/AArch64/SVE2p1/bfmaxnm.s
M llvm/test/MC/AArch64/SVE2p1/bfmin-diagnostics.s
M llvm/test/MC/AArch64/SVE2p1/bfmin.s
M llvm/test/MC/AArch64/SVE2p1/bfminnm-diagnostics.s
M llvm/test/MC/AArch64/SVE2p1/bfminnm.s
M llvm/test/MC/AArch64/SVE2p1/bfmla-diagnostics.s
M llvm/test/MC/AArch64/SVE2p1/bfmla.s
M llvm/test/MC/AArch64/SVE2p1/bfmls-diagnostics.s
M llvm/test/MC/AArch64/SVE2p1/bfmls.s
M llvm/test/MC/AArch64/SVE2p1/bfmul-diagnostics.s
M llvm/test/MC/AArch64/SVE2p1/bfmul.s
M llvm/test/MC/AArch64/SVE2p1/bfsub-diagnostics.s
M llvm/test/MC/AArch64/SVE2p1/bfsub.s
M llvm/test/MC/AArch64/SVE2p1/directive-arch-negative.s
M llvm/test/MC/AArch64/SVE2p1/directive-arch.s
M llvm/test/MC/AArch64/SVE2p1/directive-arch_extension-negative.s
M llvm/test/MC/AArch64/SVE2p1/directive-arch_extension.s
M llvm/unittests/TargetParser/TargetParserTest.cpp
Log Message:
-----------
[AArch64] Add updated FEAT_SVE_B16B16 and begin replacement of 'b16b16' flag (#101480)
This patch adds FeatureSVEB16B16 to the AArch64 backend in order to
represent the new behavior of FEAT_SVE_B16B16 (as described in the
latest [Armv9.4 extensions
documentation](https://developer.arm.com/documentation/109697/0100/Feature-descriptions/The-Armv9-4-architecture-extension?lang=en#md461-the-armv94-architecture-extension__FEAT_SVE_B16B16))
as well as a 'sve-b16b16' flag to enable it.
The predication of non-widening SVE BFloat16 instructions has changed to
require this feature, instead of the previously required and
soon-to-be-removed FeatureB16B16 which is enabled by the 'b16b16' flag.
Therefore, this change weakens the 'b16b16' flag in favour of
'sve-b16b16'. Existing tests that are effected by this have been
modified to use and/or expect 'sve-b16b16', and new tests have been
added to verify the behavior and implementation of 'sve-b16b16'.
This patch is in response to the response to the following changes.
The architecture features previously enabled by FEAT_SVE_B16B16 have
been relaxed such that it now implements:
- With FEAT_SVE2 : SVE non-widening BFloat16 instructions in
Non-streaming SVE mode
- With FEAT_SME2: SVE non-widening BFloat16 instructions when the
PE is in Streaming SVE mode and SME
Z-targeting multi-vector non-widening BFloat16 instructions.
- **It no longer implements** SME ZA-targeting non-widening
BFloat16 instructions.
The SME ZA-targeting non-widening BFloat16 instructions are implemented
by the new FEAT_SME_B16B16, **this patch does not change how this
architecture feature is enabled** ('+b16b16+sme2'). Only those that are
implemented by FEAT_SVE_B16B16 have been changed to require 'sve-b16b16'
instead of 'b16b16'.
New flags must be created to represent FEAT_SVE_B16B16 and
FEAT_SME_B16B16:
- 'sve-b16b16' enables the updated FEAT_SVE_B16B16 (described
here)
- 'sme-b16b16' will enable the new FEAT_SME_B16B16
- **This patch includes 'sve-b16b16' only**
A future patch will add 'sme-b16b16', SME ZA-targeting non-widening
BFloat16 instructions would then be guarded by '+sme-b16b16+sme2', and
'b16b16' can be removed.
Commit: f387bf86f13731eebbb9528b6812985b17d10806
https://github.com/llvm/llvm-project/commit/f387bf86f13731eebbb9528b6812985b17d10806
Author: Sayhaan Siddiqui <49014204+sayhaan at users.noreply.github.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M bolt/lib/Core/BinaryContext.cpp
M bolt/lib/Rewrite/MachORewriteInstance.cpp
M bolt/lib/Rewrite/RewriteInstance.cpp
M bolt/unittests/Core/BinaryContext.cpp
M bolt/unittests/Core/MCPlusBuilder.cpp
Log Message:
-----------
[BOLT][DWARF][NFC] Move Arch assignment out of createBinaryContext (#102054)
Moves the assignment of Arch out of createBinaryContext to prevent data
races when parallelized.
Commit: 7890a8a6d17d03dde9b861c990ad684c7aa8f347
https://github.com/llvm/llvm-project/commit/7890a8a6d17d03dde9b861c990ad684c7aa8f347
Author: Vladislav Khmelevsky <och95 at yandex.ru>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M bolt/lib/Rewrite/BinaryPassManager.cpp
Log Message:
-----------
Revert "[BOLT] Move ADRRelaxationPass (#101371)" (#102333)
This reverts commit 750b12f06badc4cdf767139c70090db62358bb44.
The pass should run after splitting phase, but before nop removal
Commit: 18c3d241219eb42b953169914a0be6ea37ad9679
https://github.com/llvm/llvm-project/commit/18c3d241219eb42b953169914a0be6ea37ad9679
Author: Ian Anderson <iana at apple.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M clang/lib/Driver/ToolChains/Darwin.cpp
A clang/test/Driver/Inputs/DriverKit23.0.sdk/SDKSettings.json
A clang/test/Driver/Inputs/MacOSX15.0.sdk/SDKSettings.json
R clang/test/Driver/Inputs/MacOSX99.0.sdk/SDKSettings.json
M clang/test/Driver/darwin-builtin-modules.c
Log Message:
-----------
[clang][modules] Enable built-in modules for the upcoming Apple releases (#102239)
The upcoming Apple SDK releases will support the clang built-in headers
being in the clang built-in modules: stop passing
-fbuiltin-headers-in-system-modules for those SDK versions.
Commit: 98a17f2e30748166beb2005a7e068fca269487d9
https://github.com/llvm/llvm-project/commit/98a17f2e30748166beb2005a7e068fca269487d9
Author: Jun Wang <jwang86 at yahoo.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-copy.mir
Log Message:
-----------
[AMDGPU] Set register bank for i1 register copies (#96155)
Set register bank in copies between a physical register and a virtual
register of s1 type.
---------
Co-authored-by: Jun Wang <jun.wang7 at amd.com>
Commit: 2a537f8b269d7319b112e07885364fe7bde5dc65
https://github.com/llvm/llvm-project/commit/2a537f8b269d7319b112e07885364fe7bde5dc65
Author: Akash Banerjee <Akash.Banerjee at amd.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td
Log Message:
-----------
Add formatting space.
Commit: 3e80e6cb2065cf56854fea01bde1cf36c1e22ac7
https://github.com/llvm/llvm-project/commit/3e80e6cb2065cf56854fea01bde1cf36c1e22ac7
Author: Akash Banerjee <Akash.Banerjee at amd.com>
Date: 2024-08-08 (Thu, 08 Aug 2024)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/test/Dialect/OpenMP/invalid.mlir
M mlir/test/Dialect/OpenMP/ops.mlir
Log Message:
-----------
Address reviewer comments. Update test cases with omp.composite checks.
Compare: https://github.com/llvm/llvm-project/compare/8d656e464eea...3e80e6cb2065
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