[all-commits] [llvm/llvm-project] 597281: [RISCV] Disable fixed length vectors with Zve32* w...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 59728193a688a21c1999579044d84d7ee0183e80
      https://github.com/llvm/llvm-project/commit/59728193a688a21c1999579044d84d7ee0183e80
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-08-08 (Thu, 08 Aug 2024)

  Changed paths:
    M llvm/docs/ReleaseNotes.rst
    M llvm/lib/Target/RISCV/RISCVSubtarget.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/zvl32b.ll

  Log Message:
  -----------
  [RISCV] Disable fixed length vectors with Zve32* without Zvl64b. (#102405)

Fixed length vectors use scalable vector containers. With Zve32* and not
Zvl64b, vscale is a 0.5 due RVVBitsPerBlock being 64.

To support this correctly we need to lower RVVBitsPerBlock to 32 and
change our type mapping. But we need to RVVBitsPerBlock to alway be
>= ELEN.  This means we need two different mapping depending on ELEN.

That is a non-trivial amount of work so disable fixed lenght vectors
without Zvl64b for now.

We had almost no tests for Zve32x without Zvl64b which is probably why
we never realized that it was broken.

Fixes #102352.



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