[all-commits] [llvm/llvm-project] 898d6e: [RISCV] Use RVA22U64Features in the definition of ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 898d6eb7be2198255c7badbbaecbce57aa8a3fb1
      https://github.com/llvm/llvm-project/commit/898d6eb7be2198255c7badbbaecbce57aa8a3fb1
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-08-07 (Wed, 07 Aug 2024)

  Changed paths:
    M clang/test/Driver/riscv-cpus.c
    M llvm/lib/Target/RISCV/RISCVProcessors.td

  Log Message:
  -----------
  [RISCV] Use RVA22U64Features in the definition of sifive-p450 and sifive-p670. (#102350)

This matches sifive-p470.

RVA22U64Features includes the Zicntr extension which was not present for
these CPUs before. I believe that was a mistake due to weird history of
the Zicntr extension. I've updated the p470 test accordingly since this
was missed there too.



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