[all-commits] [llvm/llvm-project] a0ed7d: [AArch64] Add updated FEAT_SVE_B16B16 and begin re...

Wed Aug 7 09:27:08 PDT 2024

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a0ed7d6c5fa1438983ee2c1ad25fbb53644d5eba
      https://github.com/llvm/llvm-project/commit/a0ed7d6c5fa1438983ee2c1ad25fbb53644d5eba
  Author: SpencerAbson <Spencer.Abson at arm.com>
  Date:   2024-08-07 (Wed, 07 Aug 2024)

  Changed paths:
    M clang/include/clang/Basic/arm_sve.td
    M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_clamp.c
    M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_max.c
    M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_maxnm.c
    M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_min.c
    M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_minnm.c
    M clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_bfadd.c
    M clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_bfclamp.c
    M clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_bfmax.c
    M clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c
    M clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_bfmin.c
    M clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_bfminnm.c
    M clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_bfmla.c
    M clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c
    M clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_bfmls.c
    M clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c
    M clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_bfmul.c
    M clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c
    M clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_bfsub.c
    M clang/test/Driver/print-supported-extensions-aarch64.c
    M clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_b16b16.cpp
    A clang/test/Sema/aarch64-sve2p1-intrinsics/acle_sve2p1_b16b16.cpp
    M llvm/lib/Target/AArch64/AArch64Features.td
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-max.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-min.ll
    M llvm/test/CodeGen/AArch64/sve2-min-max-clamp.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfadd.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfclamp.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfmax.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfmaxnm.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfmin.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfminnm.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfmla.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfmla_lane.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfmls.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfmls_lane.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfmul.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfmul_lane.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfsub.ll
    M llvm/test/MC/AArch64/SME2/bfclamp-diagnostics.s
    M llvm/test/MC/AArch64/SME2/bfclamp.s
    M llvm/test/MC/AArch64/SME2/bfmax-diagnostics.s
    M llvm/test/MC/AArch64/SME2/bfmax.s
    M llvm/test/MC/AArch64/SME2/bfmaxnm-diagnostics.s
    M llvm/test/MC/AArch64/SME2/bfmaxnm.s
    M llvm/test/MC/AArch64/SME2/bfmin-diagnostics.s
    M llvm/test/MC/AArch64/SME2/bfmin.s
    M llvm/test/MC/AArch64/SME2/bfminnm-diagnostics.s
    M llvm/test/MC/AArch64/SME2/bfminnm.s
    M llvm/test/MC/AArch64/SME2p1/directive-arch-negative.s
    M llvm/test/MC/AArch64/SME2p1/directive-arch.s
    M llvm/test/MC/AArch64/SME2p1/directive-arch_extension-negative.s
    M llvm/test/MC/AArch64/SME2p1/directive-arch_extension.s
    M llvm/test/MC/AArch64/SVE2p1/bfadd-diagnostics.s
    M llvm/test/MC/AArch64/SVE2p1/bfadd.s
    M llvm/test/MC/AArch64/SVE2p1/bfclamp-diagnostics.s
    M llvm/test/MC/AArch64/SVE2p1/bfclamp.s
    M llvm/test/MC/AArch64/SVE2p1/bfmax-diagnostics.s
    M llvm/test/MC/AArch64/SVE2p1/bfmax.s
    M llvm/test/MC/AArch64/SVE2p1/bfmaxnm-diagnostics.s
    M llvm/test/MC/AArch64/SVE2p1/bfmaxnm.s
    M llvm/test/MC/AArch64/SVE2p1/bfmin-diagnostics.s
    M llvm/test/MC/AArch64/SVE2p1/bfmin.s
    M llvm/test/MC/AArch64/SVE2p1/bfminnm-diagnostics.s
    M llvm/test/MC/AArch64/SVE2p1/bfminnm.s
    M llvm/test/MC/AArch64/SVE2p1/bfmla-diagnostics.s
    M llvm/test/MC/AArch64/SVE2p1/bfmla.s
    M llvm/test/MC/AArch64/SVE2p1/bfmls-diagnostics.s
    M llvm/test/MC/AArch64/SVE2p1/bfmls.s
    M llvm/test/MC/AArch64/SVE2p1/bfmul-diagnostics.s
    M llvm/test/MC/AArch64/SVE2p1/bfmul.s
    M llvm/test/MC/AArch64/SVE2p1/bfsub-diagnostics.s
    M llvm/test/MC/AArch64/SVE2p1/bfsub.s
    M llvm/test/MC/AArch64/SVE2p1/directive-arch-negative.s
    M llvm/test/MC/AArch64/SVE2p1/directive-arch.s
    M llvm/test/MC/AArch64/SVE2p1/directive-arch_extension-negative.s
    M llvm/test/MC/AArch64/SVE2p1/directive-arch_extension.s
    M llvm/unittests/TargetParser/TargetParserTest.cpp

  Log Message:
  -----------
  [AArch64] Add updated FEAT_SVE_B16B16 and begin replacement of 'b16b16' flag (#101480)

This patch adds FeatureSVEB16B16 to the AArch64 backend in order to
represent the new behavior of FEAT_SVE_B16B16 (as described in the
latest [Armv9.4 extensions
documentation](https://developer.arm.com/documentation/109697/0100/Feature-descriptions/The-Armv9-4-architecture-extension?lang=en#md461-the-armv94-architecture-extension__FEAT_SVE_B16B16))
as well as a 'sve-b16b16' flag to enable it.

The predication of non-widening SVE BFloat16 instructions has changed to
require this feature, instead of the previously required and
soon-to-be-removed FeatureB16B16 which is enabled by the 'b16b16' flag.
Therefore, this change weakens the 'b16b16' flag in favour of
'sve-b16b16'. Existing tests that are effected by this have been
modified to use and/or expect 'sve-b16b16', and new tests have been
added to verify the behavior and implementation of 'sve-b16b16'.

This patch is in response to the response to the following changes.

The architecture features previously enabled by FEAT_SVE_B16B16 have
been relaxed such that it now implements:
      - With FEAT_SVE2 : SVE non-widening BFloat16 instructions in
Non-streaming SVE mode
      - With FEAT_SME2: SVE non-widening BFloat16 instructions when the
PE is in Streaming SVE mode and SME
        Z-targeting multi-vector non-widening BFloat16 instructions.
      - **It no longer implements** SME ZA-targeting non-widening
BFloat16 instructions.   

The SME ZA-targeting non-widening BFloat16 instructions are implemented
by the new FEAT_SME_B16B16, **this patch does not change how this
architecture feature is enabled** ('+b16b16+sme2'). Only those that are
implemented by FEAT_SVE_B16B16 have been changed to require 'sve-b16b16'
instead of 'b16b16'.

New flags must be created to represent FEAT_SVE_B16B16 and
FEAT_SME_B16B16:
      - 'sve-b16b16' enables the updated FEAT_SVE_B16B16 (described
here)
      - 'sme-b16b16' will enable the new FEAT_SME_B16B16
      - **This patch includes 'sve-b16b16' only**

A future patch will add 'sme-b16b16', SME ZA-targeting non-widening
BFloat16 instructions would then be guarded by '+sme-b16b16+sme2', and
'b16b16' can be removed.

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