[all-commits] [llvm/llvm-project] 0c25f8: [RISCV] Add sifive-p470 processor (#102022)

[Michael Maitland via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0c25f85e5b88102363c0cd55e1946053d5827e99
      https://github.com/llvm/llvm-project/commit/0c25f85e5b88102363c0cd55e1946053d5827e99
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2024-08-07 (Wed, 07 Aug 2024)

  Changed paths:
    M clang/test/Driver/riscv-cpus.c
    M clang/test/Misc/target-invalid-cpu-note.c
    M llvm/docs/ReleaseNotes.rst
    M llvm/lib/Target/RISCV/RISCVProcessors.td

  Log Message:
  -----------
  [RISCV] Add sifive-p470 processor (#102022)

This is an OOO core that has a vector unit. For more information see
https://www.sifive.com/cores/performance-p450-470.

Use the existing P400 scheduler model. This model is missing accurate
vector scheduling support, but it will be added in a follow up patch.

Other tunings can come in future patches too.



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