[all-commits] [llvm/llvm-project] f7e1ef: [LLVM][ISel][SVE] Add patterns for merging reverse...

[Paul Walker via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f7e1efe8bcea14686d1c303e058f687b6ca1c79f
      https://github.com/llvm/llvm-project/commit/f7e1efe8bcea14686d1c303e058f687b6ca1c79f
  Author: Paul Walker <paul.walker at arm.com>
  Date:   2024-08-07 (Wed, 07 Aug 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/test/CodeGen/AArch64/sve-pred-selectop2.ll
    M llvm/test/CodeGen/AArch64/sve-pred-selectop3.ll

  Log Message:
  -----------
  [LLVM][ISel][SVE] Add patterns for merging reverse subtracts. (#101488)

vselect cond, ([f]sub b, a), a ==> [f]subr cond, a, b



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