[all-commits] [llvm/llvm-project] 15895d: [RISCV] Limit (and (sra x, c2), c1) -> (srli (srai...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 15895daa6862ad15bfac18b03811d066d4550713
      https://github.com/llvm/llvm-project/commit/15895daa6862ad15bfac18b03811d066d4550713
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-08-06 (Tue, 06 Aug 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll

  Log Message:
  -----------
  [RISCV] Limit (and (sra x, c2), c1) -> (srli (srai x, c2-c3), c3) isel in some cases. (#102034)

If x is a shl by 32 and c1 is an simm12, we would prefer to use a
SRAIW+ANDI. This prevents selecting the slli to a separate slli
instruction.

Fixes regression from #101868



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