[all-commits] [llvm/llvm-project] 1745c8: [MachinePipeliner] Fix instruction order with phys...

[Ryotaro KASUGA via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1745c8e08dde9f32d0f0b701d3a6a271697458eb
      https://github.com/llvm/llvm-project/commit/1745c8e08dde9f32d0f0b701d3a6a271697458eb
  Author: Ryotaro KASUGA <kasuga.ryotaro at fujitsu.com>
  Date:   2024-08-06 (Tue, 06 Aug 2024)

  Changed paths:
    M llvm/lib/CodeGen/MachinePipeliner.cpp
    A llvm/test/CodeGen/AArch64/sms-order-physreg-deps.mir

  Log Message:
  -----------
  [MachinePipeliner] Fix instruction order with physical register (#99264)

dependencies in same cycle

Dependency checks were insufficient when reordering instructions with
physical register dependencies (i.e. Anti/Output dependencies). This
could result in generating incorrect code.



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