[all-commits] [llvm/llvm-project] cfd13c: [RISCV] Improve variable scoping in custom isel fo...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: cfd13cbac12b73069c79c89bb37294f77938bb3f
      https://github.com/llvm/llvm-project/commit/cfd13cbac12b73069c79c89bb37294f77938bb3f
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-08-05 (Mon, 05 Aug 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

  Log Message:
  -----------
  [RISCV] Improve variable scoping in custom isel for ISD::AND.

Give the (and (srl/shl X, C2), C1) handling its owns private `C1` variable
it can modify using known zeros. This may be out of sync with
N1C->getZExtValue().

Add a separate const C1 for (and (sra X, C2), C1) and (and X, C).
This copy will always be in sync with N1C->getZExtValue().

Remove the IsC1Mask and IsC1ANDI variables and compute them at their
usage.

Use N1C->getSExtValue() when calling isInt. This shouldn't be a
functional change since we already checked that it was a mask. In
order for it to be a mask and a negative number, it would need to be -1
which should have been removed by DAG combine.



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