[all-commits] [llvm/llvm-project] 9884fd: [RISCV] Add Syntacore SCR4 RV32/64 processors defi...

[Anton Sidorenko via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9884fd33dbfe6dc8808a6047f29d8166a6ccb7be
      https://github.com/llvm/llvm-project/commit/9884fd33dbfe6dc8808a6047f29d8166a6ccb7be
  Author: Anton Sidorenko <anton.sidorenko at syntacore.com>
  Date:   2024-08-05 (Mon, 05 Aug 2024)

  Changed paths:
    M clang/test/Driver/riscv-cpus.c
    M clang/test/Misc/target-invalid-cpu-note.c
    M llvm/docs/ReleaseNotes.rst
    M llvm/lib/Target/RISCV/RISCVProcessors.td

  Log Message:
  -----------
  [RISCV] Add Syntacore SCR4 RV32/64 processors definition (#101321)

Syntacore SCR4 is a microcontroller-class processor core that has much
in common with SCR3. The most significant difference for compilers is F
and D extensions support. Overview: https://syntacore.com/products/scr4

Two CPUs are added:
  * 'syntacore-scr4-rv32' -- rv32imfdc
  * 'syntacore-scr4-rv64' -- rv64imafdc

Scheduling model will be added in a separate PR.

Co-authored-by: Dmitrii Petrov <dmitrii.petrov at syntacore.com>
Co-authored-by: Anton Afanasyev <anton.afanasyev at syntacore.com>



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