[all-commits] [llvm/llvm-project] a44432: [PowerPC] Add phony subregisters to cover the high...

[Stefan Pintilie via All-commits]

  Branch: refs/heads/release/19.x
  Home:   https://github.com/llvm/llvm-project
  Commit: a444324b6a5f687a235c402e05e7a79e3b17bd7b
      https://github.com/llvm/llvm-project/commit/a444324b6a5f687a235c402e05e7a79e3b17bd7b
  Author: Stefan Pintilie <stefanp at ca.ibm.com>
  Date:   2024-08-04 (Sun, 04 Aug 2024)

  Changed paths:
    M llvm/lib/Target/PowerPC/PPCRegisterInfo.td
    M llvm/test/CodeGen/PowerPC/aix-vec_insert_elt.ll
    M llvm/test/CodeGen/PowerPC/aix32-p8-scalar_vector_conversions.ll
    M llvm/test/CodeGen/PowerPC/build-vector-tests.ll
    M llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
    M llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll
    M llvm/test/CodeGen/PowerPC/combine-fneg.ll
    M llvm/test/CodeGen/PowerPC/constant-pool.ll
    M llvm/test/CodeGen/PowerPC/elf64-byval-cc.ll
    M llvm/test/CodeGen/PowerPC/fma-combine.ll
    M llvm/test/CodeGen/PowerPC/fp-strict-round.ll
    M llvm/test/CodeGen/PowerPC/frem.ll
    M llvm/test/CodeGen/PowerPC/handle-f16-storage-type.ll
    M llvm/test/CodeGen/PowerPC/ldexp.ll
    M llvm/test/CodeGen/PowerPC/p10-splatImm-CPload-pcrel.ll
    M llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
    M llvm/test/CodeGen/PowerPC/pcrel-call-linkage-leaf.ll
    M llvm/test/CodeGen/PowerPC/select_const.ll
    M llvm/test/CodeGen/PowerPC/subreg-coalescer.mir
    M llvm/test/CodeGen/PowerPC/subreg-lanemasks.mir
    M llvm/test/CodeGen/PowerPC/toc-float.ll
    M llvm/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll
    M llvm/test/CodeGen/PowerPC/vec_insert_elt.ll
    M llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll
    M llvm/test/CodeGen/PowerPC/vector-llrint.ll
    M llvm/test/CodeGen/PowerPC/vector-lrint.ll
    M llvm/test/CodeGen/PowerPC/vector-reduce-fadd.ll
    M llvm/test/CodeGen/PowerPC/vector-reduce-fmax.ll
    M llvm/test/CodeGen/PowerPC/vector-reduce-fmin.ll
    M llvm/test/CodeGen/PowerPC/vector-reduce-fmul.ll
    M llvm/test/CodeGen/PowerPC/vsx.ll

  Log Message:
  -----------
  [PowerPC] Add phony subregisters to cover the high half of the VSX registers. (#94628)

On PowerPC there are 128 bit VSX registers. These registers are half
overlapped with 64 bit floating point registers (FPR). The 64 bit half
of the VXS register that does not overlap with the FPR does not overlap
with any other register class. The FPR are the only subregisters of the
VSX registers but they do not fully cover the 128 bit super register.
This leads to incorrect lane masks being created.

This patch adds phony registers for the other half of the VSX registers
in order to fully cover them and to make sure that the lane masks are
not the same for the VSX and the floating point register.

(cherry picked from commit 53c37f300dd1b450671f2aee4cc649c380adb5ad)



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