[all-commits] [llvm/llvm-project] 766f68: [RISCV] Invert if conditions in the switch in RISC...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 766f68d17ab1b12a46324d8b526f753cd1a353d3
      https://github.com/llvm/llvm-project/commit/766f68d17ab1b12a46324d8b526f753cd1a353d3
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-08-03 (Sat, 03 Aug 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

  Log Message:
  -----------
  [RISCV] Invert if conditions in the switch in RISCVDAGToDAGISel::hasAllNBitUsers. NFC

Make "break" consistently the "if" body and the "return false" the
last thing in each case.

This makes it easier to add different conditions for different operands
of some instructions and makes everything more consistent.



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