[all-commits] [llvm/llvm-project] 4aac78: [RISCV] Generalize existing SRA combine to fix #10...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4aac78dd4a89f16657c162320e3a720437cb7284
      https://github.com/llvm/llvm-project/commit/4aac78dd4a89f16657c162320e3a720437cb7284
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-08-02 (Fri, 02 Aug 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rv32zbb.ll
    M llvm/test/CodeGen/RISCV/rv64zbb.ll

  Log Message:
  -----------
  [RISCV] Generalize existing SRA combine to fix #101040. (#101610)

We already had a DAG combine for (sra (sext_inreg (shl X, C1), i32), C2)
-> (sra (shl X, C1+32), C2+32) that we used for RV64. This patch
generalizes it to other sext_inregs for both RV32 and RV64.
    
Fixes #101040.



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