[all-commits] [llvm/llvm-project] 3a4c7c: Forward declare OSSpinLockLock on MacOS since it's...
Fangrui Song via All-commits
all-commits at lists.llvm.org
Thu Aug 1 09:15:30 PDT 2024
Branch: refs/heads/users/MaskRay/spr/elf-support-relocatable-files-using-crel
Home: https://github.com/llvm/llvm-project
Commit: 3a4c7cc56c07b2db9010c2228fc7cb2a43dd9b2d
https://github.com/llvm/llvm-project/commit/3a4c7cc56c07b2db9010c2228fc7cb2a43dd9b2d
Author: Amara Emerson <amara at apple.com>
Date: 2024-07-31 (Wed, 31 Jul 2024)
Changed paths:
M compiler-rt/lib/rtsan/rtsan_interceptors.cpp
Log Message:
-----------
Forward declare OSSpinLockLock on MacOS since it's not shipped on the system. (#101392)
Fixes build errors on some SDKs.
rdar://132607572
Commit: 307d1249ea635a78fcd347a65ddaa395cf64130e
https://github.com/llvm/llvm-project/commit/307d1249ea635a78fcd347a65ddaa395cf64130e
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-07-31 (Wed, 31 Jul 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/test/CodeGen/LoongArch/ucmp.ll
M llvm/test/CodeGen/RISCV/ucmp.ll
Log Message:
-----------
[LegalizeTypes][RISCV][LoongArch] Optimize promotion of ucmp. (#101366)
ucmp can be promoted with either sext or zext. RISC-V and LoongArch
prefer sext for promoting i32 to i64 unless the inputs are known to be
zero extended already.
This patch uses the existing SExtOrZExtPromotedOperands function that is
used by SETCC promotion to intelligently handle this.
Commit: 1c5f6cfc352c3bd2a4faa0e3aebb4028b557a5e7
https://github.com/llvm/llvm-project/commit/1c5f6cfc352c3bd2a4faa0e3aebb4028b557a5e7
Author: Justin Bogner <mail at justinbogner.com>
Date: 2024-07-31 (Wed, 31 Jul 2024)
Changed paths:
M llvm/lib/Target/DirectX/DXILPrepare.cpp
M llvm/lib/Target/DirectX/DXILPrettyPrinter.cpp
M llvm/lib/Target/DirectX/DXILResourceAnalysis.cpp
M llvm/lib/Target/DirectX/DXILResourceAnalysis.h
M llvm/lib/Target/DirectX/DXILTranslateMetadata.cpp
M llvm/lib/Target/DirectX/DirectX.h
M llvm/lib/Target/DirectX/DirectXPassRegistry.def
M llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
M llvm/test/CodeGen/DirectX/UAVMetadata.ll
M llvm/test/CodeGen/DirectX/cbuf.ll
Log Message:
-----------
[DirectX] Rename backend DXIL resource analysis passes to DXILResourceMD*. NFC
These passes will be replaced soon as we move to the target extension based
resource handling in the DirectX backend, but removing them now before the
replacement stuff is all up and running would be very disruptive. However, we
do need to move these passes out of the way to avoid symbol conflicts with the
new DXILResourceAnalysis in the Analysis library.
Note: I tried an even simpler hack in #100698 but it doesn't really work. A
rename is the most expedient path forward here.
Pull Request: https://github.com/llvm/llvm-project/pull/101393
Commit: 5dbbc3b14bb04ef4bf2cbf4c23008f94f4253704
https://github.com/llvm/llvm-project/commit/5dbbc3b14bb04ef4bf2cbf4c23008f94f4253704
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-07-31 (Wed, 31 Jul 2024)
Changed paths:
M lldb/source/Commands/CommandObjectBreakpointCommand.cpp
M lldb/source/Commands/CommandObjectDisassemble.cpp
M lldb/source/Commands/CommandObjectTarget.cpp
M lldb/source/Commands/CommandObjectWatchpoint.cpp
M lldb/source/Commands/CommandObjectWatchpoint.h
M lldb/source/Commands/CommandObjectWatchpointCommand.cpp
Log Message:
-----------
[lldb] Use Target references instead of pointers in CommandObject (NFC)
The GetTarget helper returns a Target reference so there's reason to
convert it to a pointer and check its validity.
Commit: 87af9ee870ad7ca93abced0b09459c3760dec891
https://github.com/llvm/llvm-project/commit/87af9ee870ad7ca93abced0b09459c3760dec891
Author: Yeting Kuo <46629943+yetingk at users.noreply.github.com>
Date: 2024-08-01 (Thu, 01 Aug 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll
Log Message:
-----------
[RISCV] Use experimental.vp.splat to splat specific vector length elements. (#101329)
Previously, llvm IR is hard to create a scalable vector splat with a
specific vector length, so we use riscv.vmv.v.x and riscv.vmv.v.f to do
this work. But the two rvv intrinsics needs strict type constraint which
can not support fixed vector types and illegal vector types. Using
vp.splat could preserve old functionality and also generate more
optimized code for vector types and illegal vectors.
This patch also fixes crash for getEVT not serving ptr types.
Commit: e2c74aa535752cd6cf098731608d26275d1e40ac
https://github.com/llvm/llvm-project/commit/e2c74aa535752cd6cf098731608d26275d1e40ac
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-07-31 (Wed, 31 Jul 2024)
Changed paths:
M llvm/include/llvm/CodeGen/ValueTypes.td
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
M llvm/utils/TableGen/VTEmitter.cpp
Log Message:
-----------
[TableGen][MVT] Lower the maximum 16-bit MVT from 16384 to 511. (#101401)
MachineValueTypeSet in tablegen allocates an array with a bit per MVT.
This used to be 256 bits, with the introduction of 16-bit MVT it
ballooned to 65536 bits. I suspect this is increasing the memory usage
of many of the data structures used by CodeGenDAGPatterns.
Since we don't need the full 16-bit range yet, this patch proposes
lowering the maximum MVT to 511 and using only 512 bits for
MachineValueTypeSet's storage.
Commit: a1ba4fb4516a33bd61b8219e2fc46ba3c1787460
https://github.com/llvm/llvm-project/commit/a1ba4fb4516a33bd61b8219e2fc46ba3c1787460
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-07-31 (Wed, 31 Jul 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
Log Message:
-----------
[RISCV][GISel] Slightly simplify the regbank selection for G_LOAD/STORE. NFC (#101431)
Merge the isVector early out with the previous check for isVector.
Commit: bc6834f5c70daca7ec321398a16891800b1c2bd8
https://github.com/llvm/llvm-project/commit/bc6834f5c70daca7ec321398a16891800b1c2bd8
Author: Andrea 🦈 <anfaulds at amd.com>
Date: 2024-07-31 (Wed, 31 Jul 2024)
Changed paths:
M mlir/utils/spirv/gen_spirv_dialect.py
Log Message:
-----------
[mlir][spirv] Fix tablegen generator script's stripping of prefixes (#101378)
This script looks for existing definitions with the `SPIRV_` prefix, so
that it can preserve them when updating the file. When the commit
2d628330482e49d36744cb8f3fb5047cfeae6c56 changed the prefix from `SPV_`,
the number of characters to strip from matched names was not updated,
which broke this feature. This commit fixes remaining cases that weren't
fixed by 339c87a8a086347bd8b5aae8b5bc43fc1c155cc1.
The relationship of this script to the files it is meant to maintain is
still bitrotten in other ways.
Commit: e6aeb3f4daea0ffd43930c63f9b9a7668b915fd9
https://github.com/llvm/llvm-project/commit/e6aeb3f4daea0ffd43930c63f9b9a7668b915fd9
Author: lifengxiang1025 <lifengxiang at kuaishou.com>
Date: 2024-08-01 (Thu, 01 Aug 2024)
Changed paths:
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/test/Transforms/MemProfContextDisambiguation/tailcall.ll
Log Message:
-----------
[MemProf] Fix when function has indirect call (#101170)
When function has indirect call in LTO mode, it causes `assert(Alias)`
in `findProfiledCalleeThroughTailCalls`
Commit: 9227fd74e49b045baba910cb07ee93b2c660d267
https://github.com/llvm/llvm-project/commit/9227fd74e49b045baba910cb07ee93b2c660d267
Author: vporpo <vporpodas at google.com>
Date: 2024-07-31 (Wed, 31 Jul 2024)
Changed paths:
M llvm/unittests/SandboxIR/SandboxIRTest.cpp
Log Message:
-----------
[SandboxIR][NFC] Factor out common test for CastInst subclasses (#101410)
The tests for most CastInst sub-classes, except AddrSpaceCastInst, are
very similar.
This patch creates a common template function for all of them.
Commit: 42c413b48917491efc5372752c6ad245530939f5
https://github.com/llvm/llvm-project/commit/42c413b48917491efc5372752c6ad245530939f5
Author: Hideto Ueno <uenoku.tokotoko at gmail.com>
Date: 2024-08-01 (Thu, 01 Aug 2024)
Changed paths:
M mlir/lib/Transforms/OpStats.cpp
M mlir/lib/Transforms/PrintIR.cpp
M mlir/lib/Transforms/ViewOpGraph.cpp
Log Message:
-----------
[mlir][Transforms] Preserve all analysis in print passes (#101315)
PrintIRPass, PrintOpStatsPass and PrintOpGraphPass don't mutate IR so
preserve all analysis to save computation resource a bit.
Commit: ed12f80ff0a8d304d10245c7bfb9f6af4a5c968c
https://github.com/llvm/llvm-project/commit/ed12f80ff0a8d304d10245c7bfb9f6af4a5c968c
Author: Job Henandez Lara <hj93 at protonmail.com>
Date: 2024-07-31 (Wed, 31 Jul 2024)
Changed paths:
M libc/config/gpu/entrypoints.txt
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/arm/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/math/index.rst
M libc/spec/stdc.td
M libc/src/math/CMakeLists.txt
M libc/src/math/generic/CMakeLists.txt
A libc/src/math/generic/getpayload.cpp
A libc/src/math/generic/getpayloadf.cpp
A libc/src/math/generic/getpayloadf128.cpp
A libc/src/math/getpayload.h
A libc/src/math/getpayloadf.h
A libc/src/math/getpayloadf128.h
M libc/test/src/math/smoke/CMakeLists.txt
A libc/test/src/math/smoke/getpayload_test.cpp
A libc/test/src/math/smoke/getpayloadf128_test.cpp
A libc/test/src/math/smoke/getpayloadf_test.cpp
Log Message:
-----------
[libc][math][c23] add entrypoints and tests for getpayload{,f,f128} (#101285)
Commit: 430b90f04533b099d788db2668176038be38c53b
https://github.com/llvm/llvm-project/commit/430b90f04533b099d788db2668176038be38c53b
Author: Wu Yingcong <yingcong.wu at intel.com>
Date: 2024-08-01 (Thu, 01 Aug 2024)
Changed paths:
M llvm/lib/Transforms/Instrumentation/NumericalStabilitySanitizer.cpp
Log Message:
-----------
[nsan][NFC] Use cast when dyn_cast is not needed. (#101147)
Use `cast` instead to replace `dyn_cast` when `dyn_cast` is not
needed/not checked.
Commit: 27b608055f8e86e2decea519e6dc1ab6aff4824e
https://github.com/llvm/llvm-project/commit/27b608055f8e86e2decea519e6dc1ab6aff4824e
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2024-08-01 (Thu, 01 Aug 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.h
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/lib/Target/RISCV/RISCVSubtarget.h
A llvm/test/CodeGen/RISCV/riscv-tail-dup-size.ll
Log Message:
-----------
[RISCV] Increase default tail duplication threshold to 6 at -O3 (#98873)
This is just like AArch64.
Changing the threshold to 6 will increase the code size, but will
also decrease unconditional branches. CPUs with wide fetch/issue units
can benefit from it.
The value 6 may be debatable, we can set it to `SchedModel.IssueWidth`.
Commit: 991a6215a9ccd99eb91d2b2d46b58c2fd648c263
https://github.com/llvm/llvm-project/commit/991a6215a9ccd99eb91d2b2d46b58c2fd648c263
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-07-31 (Wed, 31 Jul 2024)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
Log Message:
-----------
[TargetLowering] Remove weird use of MVT::isVoid in an assert. (#101436)
At the time this was written there were no vector types in MVT. The
order was:
-scalar integer types
-scalar FP types
-isVoid
I believe this isVoid check was to catch walking off the end of the
scalar FP types. While the isInteger()==isInteger caught walking off the
end of scalar integer types.
These days we have:
-scalar integer types
-scalar FP types
-fixed vector integer types
-fixed vector FP types
-scalable vector integer types
-scalable vector FP types.
-Glue
-isVoid
So checking isVoid doesn't detect what it used to. I've changed it to
check isFloatingPoint() == isFloatingPoint() instead.
Commit: fb97b4f96217442c684a940558135ffbfe45b756
https://github.com/llvm/llvm-project/commit/fb97b4f96217442c684a940558135ffbfe45b756
Author: Amir Ayupov <aaupov at fb.com>
Date: 2024-07-31 (Wed, 31 Jul 2024)
Changed paths:
M bolt/lib/Rewrite/RewriteInstance.cpp
A bolt/test/timers.c
Log Message:
-----------
[BOLT][NFC] Add timers for MetadataManager invocations
Test Plan: added bolt/test/timers.c
Reviewers: ayermolo, maksfb, rafaelauler, dcci
Reviewed By: dcci
Pull Request: https://github.com/llvm/llvm-project/pull/101267
Commit: 3f51bec466c4b67814a7877859ba3eeb5f80da7a
https://github.com/llvm/llvm-project/commit/3f51bec466c4b67814a7877859ba3eeb5f80da7a
Author: Amir Ayupov <aaupov at fb.com>
Date: 2024-07-31 (Wed, 31 Jul 2024)
Changed paths:
M bolt/lib/Rewrite/RewriteInstance.cpp
M bolt/test/timers.c
Log Message:
-----------
[BOLT][NFC] Print timers in perf2bolt invocation
When BOLT is run in AggregateOnly mode (perf2bolt), it exits with code
zero so destructors are not run thus TimerGroup never prints the timers.
Add explicit printing just before the exit to honor options requesting
timers (`--time-rewrite`, `--time-aggr`).
Test Plan: updated bolt/test/timers.c
Reviewers: ayermolo, maksfb, rafaelauler, dcci
Reviewed By: dcci
Pull Request: https://github.com/llvm/llvm-project/pull/101270
Commit: 9d068f7137a2ad732d008df46eb71aadb0cd8a8e
https://github.com/llvm/llvm-project/commit/9d068f7137a2ad732d008df46eb71aadb0cd8a8e
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-07-31 (Wed, 31 Jul 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/vle.ll
M llvm/test/CodeGen/RISCV/rvv/vse.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-vp-bf16.ll
Log Message:
-----------
[RISCV] Remove Zfbfmin from some vector test RUN lines. NFC
Commit: 86815a1842d308521f46048bb9ed08e47c0d8357
https://github.com/llvm/llvm-project/commit/86815a1842d308521f46048bb9ed08e47c0d8357
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-08-01 (Thu, 01 Aug 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/crash-stack-address-O0.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.gfx.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement-stack-lower.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frame-index.mir
M llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
Log Message:
-----------
AMDGPU/GlobalISel: Permit mapping G_FRAME_INDEX to sgprs (#101325)
eliminateFrameIndex should now properly handle materializing
frame indices in SGPRs, so treat this like the other constant
operand types.
On average this will produce worse code; we need to detect
VGPR uses, and improve SGPR->VGPR frame index folds.
Commit: f8ad6e9ad15cc60b0390092e15d465d1ac59b9fd
https://github.com/llvm/llvm-project/commit/f8ad6e9ad15cc60b0390092e15d465d1ac59b9fd
Author: Fangrui Song <i at maskray.me>
Date: 2024-08-01 (Thu, 01 Aug 2024)
Changed paths:
M bolt/lib/Rewrite/RewriteInstance.cpp
A bolt/test/timers.c
M compiler-rt/lib/rtsan/rtsan_interceptors.cpp
M libc/config/gpu/entrypoints.txt
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/arm/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/math/index.rst
M libc/spec/stdc.td
M libc/src/math/CMakeLists.txt
M libc/src/math/generic/CMakeLists.txt
A libc/src/math/generic/getpayload.cpp
A libc/src/math/generic/getpayloadf.cpp
A libc/src/math/generic/getpayloadf128.cpp
A libc/src/math/getpayload.h
A libc/src/math/getpayloadf.h
A libc/src/math/getpayloadf128.h
M libc/test/src/math/smoke/CMakeLists.txt
A libc/test/src/math/smoke/getpayload_test.cpp
A libc/test/src/math/smoke/getpayloadf128_test.cpp
A libc/test/src/math/smoke/getpayloadf_test.cpp
M lld/ELF/MarkLive.cpp
M lldb/source/Commands/CommandObjectBreakpointCommand.cpp
M lldb/source/Commands/CommandObjectDisassemble.cpp
M lldb/source/Commands/CommandObjectTarget.cpp
M lldb/source/Commands/CommandObjectWatchpoint.cpp
M lldb/source/Commands/CommandObjectWatchpoint.h
M lldb/source/Commands/CommandObjectWatchpointCommand.cpp
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/CodeGen/ValueTypes.td
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/DirectX/DXILPrepare.cpp
M llvm/lib/Target/DirectX/DXILPrettyPrinter.cpp
M llvm/lib/Target/DirectX/DXILResourceAnalysis.cpp
M llvm/lib/Target/DirectX/DXILResourceAnalysis.h
M llvm/lib/Target/DirectX/DXILTranslateMetadata.cpp
M llvm/lib/Target/DirectX/DirectX.h
M llvm/lib/Target/DirectX/DirectXPassRegistry.def
M llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
M llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
M llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.h
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/lib/Target/RISCV/RISCVSubtarget.h
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/lib/Transforms/Instrumentation/NumericalStabilitySanitizer.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/crash-stack-address-O0.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.gfx.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement-stack-lower.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frame-index.mir
M llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
M llvm/test/CodeGen/DirectX/UAVMetadata.ll
M llvm/test/CodeGen/DirectX/cbuf.ll
M llvm/test/CodeGen/LoongArch/ucmp.ll
A llvm/test/CodeGen/RISCV/riscv-tail-dup-size.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/vle.ll
M llvm/test/CodeGen/RISCV/rvv/vse.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-vp-bf16.ll
M llvm/test/CodeGen/RISCV/ucmp.ll
M llvm/test/Transforms/MemProfContextDisambiguation/tailcall.ll
M llvm/unittests/SandboxIR/SandboxIRTest.cpp
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
M llvm/utils/TableGen/VTEmitter.cpp
M mlir/lib/Transforms/OpStats.cpp
M mlir/lib/Transforms/PrintIR.cpp
M mlir/lib/Transforms/ViewOpGraph.cpp
M mlir/utils/spirv/gen_spirv_dialect.py
Log Message:
-----------
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