[all-commits] [llvm/llvm-project] 04e843: [RISCV] Add vector bf16 load/store intrinsic tests...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 04e8433165de66fa8514ef2db53d9f6dd7c244c0
      https://github.com/llvm/llvm-project/commit/04e8433165de66fa8514ef2db53d9f6dd7c244c0
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-07-31 (Wed, 31 Jul 2024)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/vle.ll
    M llvm/test/CodeGen/RISCV/rvv/vleff.ll
    M llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vloxei.ll
    M llvm/test/CodeGen/RISCV/rvv/vlse.ll
    M llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vluxei.ll
    M llvm/test/CodeGen/RISCV/rvv/vse.ll
    M llvm/test/CodeGen/RISCV/rvv/vsoxei-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsoxei.ll
    M llvm/test/CodeGen/RISCV/rvv/vsse.ll
    M llvm/test/CodeGen/RISCV/rvv/vsuxei-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsuxei.ll

  Log Message:
  -----------
  [RISCV] Add vector bf16 load/store intrinsic tests. NFC

This adds bf16 to the unit stride, strided, and index load and
store intrinsics. clang already assumes these work with Zvfbfmin.


  Commit: 84a3739ac072c95af9fa80e36d9e0f52d11e28eb
      https://github.com/llvm/llvm-project/commit/84a3739ac072c95af9fa80e36d9e0f52d11e28eb
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-07-31 (Wed, 31 Jul 2024)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/vle.ll
    M llvm/test/CodeGen/RISCV/rvv/vleff.ll
    M llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vloxei.ll
    M llvm/test/CodeGen/RISCV/rvv/vlse.ll
    M llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vluxei.ll
    M llvm/test/CodeGen/RISCV/rvv/vse.ll
    M llvm/test/CodeGen/RISCV/rvv/vsoxei-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsoxei.ll
    M llvm/test/CodeGen/RISCV/rvv/vsse.ll
    M llvm/test/CodeGen/RISCV/rvv/vsuxei.ll

  Log Message:
  -----------
  [RISCV] Replace Zvfh with Zvfhmin on vector load/store intrinsic tests. NFC

clang uses these with Zvfhmin so we should test them.


Compare: https://github.com/llvm/llvm-project/compare/972c02929ba6...84a3739ac072

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