[all-commits] [llvm/llvm-project] 1c66ef: [GISEL][RISCV] RegBank Select for Scalable Vector ...

[Jiahan Xie via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1c66ef915710fd4450f85ebb0486695e9bbc4dfc
      https://github.com/llvm/llvm-project/commit/1c66ef915710fd4450f85ebb0486695e9bbc4dfc
  Author: Jiahan Xie <88367305+jiahanxie353 at users.noreply.github.com>
  Date:   2024-07-31 (Wed, 31 Jul 2024)

  Changed paths:
    M llvm/lib/CodeGen/RegisterBankInfo.cpp
    M llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
    A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/load.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/store.mir

  Log Message:
  -----------
  [GISEL][RISCV] RegBank Select for Scalable Vector Load/Store (#99932)

This patch supports GlobalISel for register bank selection for scalable vector
load and store instructions in RISC-V



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