[all-commits] [llvm/llvm-project] 63cf3d: [RegisterCoalescer] Fix SUBREG_TO_REG handling in ...

[Stefan Pintilie via All-commits]

  Branch: refs/heads/release/19.x
  Home:   https://github.com/llvm/llvm-project
  Commit: 63cf3d4fb07a4e2c484ae44cec5df2c273fc7fff
      https://github.com/llvm/llvm-project/commit/63cf3d4fb07a4e2c484ae44cec5df2c273fc7fff
  Author: Stefan Pintilie <stefanp at ca.ibm.com>
  Date:   2024-07-31 (Wed, 31 Jul 2024)

  Changed paths:
    M llvm/lib/CodeGen/RegisterCoalescer.cpp
    A llvm/test/CodeGen/PowerPC/subreg-coalescer.mir
    A llvm/test/CodeGen/X86/subreg-fail.mir

  Log Message:
  -----------
  [RegisterCoalescer] Fix SUBREG_TO_REG handling in the RegisterCoalescer. (#96839)

The issue with the handling of the SUBREG_TO_REG is that we don't join
the subranges correctly when we join live ranges across the
SUBREG_TO_REG. For example when joining across this:
```
32B	  %2:gr64_nosp = SUBREG_TO_REG 0, %0:gr32, %subreg.sub_32bit
```
we want to join these live ranges:
```
%0 [16r,32r:0) 0 at 16r  weight:0.000000e+00
%2 [32r,112r:0) 0 at 32r  weight:0.000000e+00
```
Before the fix the range for the resulting merged `%2` is:
```
%2 [16r,112r:0) 0 at 16r  weight:0.000000e+00
```
After the fix it is now this:
```
%2 [16r,112r:0) 0 at 16r  L000000000000000F [16r,112r:0) 0 at 16r  weight:0.000000e+00
```

Two tests are added to this fix. The X86 test fails without the patch.
The PowerPC test passes with and without the patch but is added as a way
track future possible failures when register classes are changed in a
future patch.

(cherry picked from commit 26fa399012da00fbf806f50ad72a3b5f0ee63eab)



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