[all-commits] [llvm/llvm-project] 5b41b6: AMDGPU/GlobalISel: Partially move constant selecti...

[Matt Arsenault via All-commits]

  Branch: refs/heads/users/arsenm/amdgpu-globalisel-partially-move-constant-selection-to-patterns
  Home:   https://github.com/llvm/llvm-project
  Commit: 5b41b6dedeb8b3b3a629dcdee0858d58dea89ae4
      https://github.com/llvm/llvm-project/commit/5b41b6dedeb8b3b3a629dcdee0858d58dea89ae4
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2024-07-30 (Tue, 30 Jul 2024)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
    M llvm/lib/Target/AMDGPU/SIInstrInfo.td
    M llvm/lib/Target/AMDGPU/SIInstructions.td
    M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/floor.f64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fconstant.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-constant.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global-saddr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptrmask.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mfma.gfx90a.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.rsq.clamp.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
    M llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
    M llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll
    M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-memcpy.ll
    M llvm/test/CodeGen/AMDGPU/mmra.ll
    M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
    M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
    M llvm/test/CodeGen/AMDGPU/roundeven.ll
    M llvm/test/CodeGen/AMDGPU/scalar_to_vector_v2x16.ll
    M llvm/test/CodeGen/AMDGPU/vgpr-spill-placement-issue61083.ll

  Log Message:
  -----------
  AMDGPU/GlobalISel: Partially move constant selection to patterns

This is still relying on the manual code for splitting 64-bit
constants, and handling pointers.

We were missing some of the tablegen patterns for all immediate types,
so this has some side effect DAG path improvements. This also reduces
the diff in the 2 selector outputs.


  Commit: 810428748975036e914b177a289f19bb6b49acd8
      https://github.com/llvm/llvm-project/commit/810428748975036e914b177a289f19bb6b49acd8
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2024-07-30 (Tue, 30 Jul 2024)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIInstructions.td
    M llvm/test/CodeGen/AMDGPU/bf16.ll

  Log Message:
  -----------
  different true16/fake16 patterns


Compare: https://github.com/llvm/llvm-project/compare/1e492ae64fcb...810428748975

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