[all-commits] [llvm/llvm-project] ad8026: [RISCV] Qualify all XCV predicates with !is64Bit. ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ad8026587464f29e53c673e892d646a4b94f138b
      https://github.com/llvm/llvm-project/commit/ad8026587464f29e53c673e892d646a4b94f138b
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-07-29 (Mon, 29 Jul 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

  Log Message:
  -----------
  [RISCV] Qualify all XCV predicates with !is64Bit. (#101074)

The tablegen patterns all have isRV32. I did not check if any of them
could naively support RV64.

Fixes #101067 and probably other bugs like it we haven't found yet.



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