[all-commits] [llvm/llvm-project] a79db9: [GISel][TableGen] Generate getRegBankFromRegClass ...
Kai Nacke via All-commits
all-commits at lists.llvm.org
Thu Jul 25 06:42:18 PDT 2024
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: a79db96ec0decca4fe45579e039cf5589345b3ed
https://github.com/llvm/llvm-project/commit/a79db96ec0decca4fe45579e039cf5589345b3ed
Author: Kai Nacke <kai.peter.nacke at ibm.com>
Date: 2024-07-25 (Thu, 25 Jul 2024)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.h
M llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
M llvm/lib/Target/ARM/ARMRegisterBankInfo.h
M llvm/lib/Target/M68k/GISel/M68kRegisterBankInfo.cpp
M llvm/lib/Target/M68k/GISel/M68kRegisterBankInfo.h
M llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
M llvm/lib/Target/Mips/MipsRegisterBankInfo.h
M llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
M llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.h
M llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
M llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.h
M llvm/lib/Target/SPIRV/SPIRVRegisterBankInfo.cpp
M llvm/lib/Target/X86/GISel/X86RegisterBankInfo.cpp
M llvm/lib/Target/X86/GISel/X86RegisterBankInfo.h
A llvm/test/TableGen/RegBankFromRegClass.td
M llvm/utils/TableGen/RegisterBankEmitter.cpp
Log Message:
-----------
[GISel][TableGen] Generate getRegBankFromRegClass (#99896)
Generating the mapping from a register class to a register bank is
complex:
- there can be lots of register classes
- the mapping may be ambiguos
- a register class can span several register banks (e.g. a register
class containing all registers)
- the type information is not enough to decide which register bank to
map to (e.g. a register class containing floating point and vector
registers, and all register can represent a f64 value)
The approach taken here is to encode the register banks in an array
indexed by the ID of the register class. To save space, the entries are
packed into chunks of size 2^n.
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