[all-commits] [llvm/llvm-project] 411bb6: [RISCV] Fix InsnCI register type (#100113)

Sudharsan Veeravalli via All-commits all-commits at lists.llvm.org
Wed Jul 24 07:35:08 PDT 2024


  Branch: refs/heads/release/19.x
  Home:   https://github.com/llvm/llvm-project
  Commit: 411bb691fe4c69bf167b3a03b052c094687f99ce
      https://github.com/llvm/llvm-project/commit/411bb691fe4c69bf167b3a03b052c094687f99ce
  Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
  Date:   2024-07-24 (Wed, 24 Jul 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoC.td
    M llvm/test/MC/RISCV/insn_c.s

  Log Message:
  -----------
  [RISCV] Fix InsnCI register type (#100113)

According to the spec the CI type instructions can take any of the 32
RVI registers.

Fixes #100112

(cherry picked from commit 1ebfc81a91194c000ac70b4ea53891cc956aa6eb)



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