[all-commits] [llvm/llvm-project] f8cdff: [AArch64] Lower scalable i1 vector add reduction t...

[Max Beck-Jones via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f8cdffab60268ac6517177eab9a0c4cd17b3b20b
      https://github.com/llvm/llvm-project/commit/f8cdffab60268ac6517177eab9a0c4cd17b3b20b
  Author: Max Beck-Jones <max.beck-jones at arm.com>
  Date:   2024-07-23 (Tue, 23 Jul 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    A llvm/test/CodeGen/AArch64/sve-i1-add-reduce.ll

  Log Message:
  -----------
  [AArch64] Lower scalable i1 vector add reduction to cntp (#100118)

Doing an add reduction on a vector of i1 elements is the same as
counting the number of set elements so such a reduction can be lowered
to a cntp instruction. This saves a number of instructions over
performing a UADDV. This patch only handles straightforward cases (i.e.
when vectors are not split).



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