[all-commits] [llvm/llvm-project] 1ebfc8: [RISCV] Fix InsnCI register type (#100113)

[Sudharsan Veeravalli via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1ebfc81a91194c000ac70b4ea53891cc956aa6eb
      https://github.com/llvm/llvm-project/commit/1ebfc81a91194c000ac70b4ea53891cc956aa6eb
  Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
  Date:   2024-07-23 (Tue, 23 Jul 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoC.td
    M llvm/test/MC/RISCV/insn_c.s

  Log Message:
  -----------
  [RISCV] Fix InsnCI register type (#100113)

According to the spec the CI type instructions can take any of the 32
RVI registers.

Fixes #100112



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