[all-commits] [llvm/llvm-project] 4d8e42: [NVPTX] enforce signed 32 bit type for immediate o...

[Alex MacLean via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4d8e42ea6a89c73f90941fd1b6e899912e31dd34
      https://github.com/llvm/llvm-project/commit/4d8e42ea6a89c73f90941fd1b6e899912e31dd34
  Author: Alex MacLean <amaclean at nvidia.com>
  Date:   2024-07-20 (Sat, 20 Jul 2024)

  Changed paths:
    M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
    M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
    A llvm/test/CodeGen/NVPTX/addr-mode.ll
    M llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep.ll

  Log Message:
  -----------
  [NVPTX] enforce signed 32 bit type for immediate offset (#99682)

The NVPTX ISA states that an immOff must fit in a signed 32-bit integer
(https://docs.nvidia.com/cuda/parallel-thread-execution/#addresses-as-operands):

> `[reg+immOff]`
>
> a sum of register `reg` containing a byte address plus a constant
> integer byte offset (signed, 32-bit).
> 
> `[var+immOff]`
>
> a sum of address of addressable variable `var` containing a byte
> address plus a constant integer byte offset (signed, 32-bit).

Currently we do not consider this constraint, meaning that in some edge
cases we generate invalid PTX when a value is offset by a very large
immediate.



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