[all-commits] [llvm/llvm-project] b7b007: [AArch64][SVE] Improve code quality of vector unsi...

[Dinar Temirbulatov via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b7b0071680e60c60da9d4d858f944fd95d76fd42
      https://github.com/llvm/llvm-project/commit/b7b0071680e60c60da9d4d858f944fd95d76fd42
  Author: Dinar Temirbulatov <Dinar.Temirbulatov at arm.com>
  Date:   2024-07-19 (Fri, 19 Jul 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/double_reduct.ll
    M llvm/test/CodeGen/AArch64/sve-doublereduct.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-vector-zext.ll
    M llvm/test/CodeGen/AArch64/sve-int-reduce.ll
    A llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-reductions.ll
    M llvm/test/CodeGen/AArch64/vecreduce-add.ll

  Log Message:
  -----------
  [AArch64][SVE] Improve code quality of vector unsigned/signed add reductions. (#97339)

For SVE we don't have to zero extend and sum part of the result before
issuing UADDV instruction. Also this change allows to handle bigger than
a legal vector type more efficiently and lower a fixed-length vector
type to SVE's UADDV where appropriate.



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