[all-commits] [llvm/llvm-project] 092dd9: [AArch64] Remove redundant instructions in int-to-...

[SpencerAbson via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 092dd9ca2d5149e3252098610c73e4fa42d831b9
      https://github.com/llvm/llvm-project/commit/092dd9ca2d5149e3252098610c73e4fa42d831b9
  Author: SpencerAbson <Spencer.Abson at arm.com>
  Date:   2024-07-19 (Fri, 19 Jul 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
    M llvm/test/CodeGen/AArch64/fixed-point-conv-vec-pat.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-to-fp.ll

  Log Message:
  -----------
  [AArch64] Remove redundant instructions in int-to-fp of lowest vector… (#98602)

… element. 
When converting the lowest element (that in lane 0) of a vector from an
integer to a floating-point value, LLVM should select the SIMD scalar
variant of CVTF
(https://developer.arm.com/documentation/dui0801/g/A64-SIMD-Scalar-Instructions/SCVTF--scalar--integer-)
to avoid the FPR to GPR register transfers that are required to use the
general floating-point variant
(https://developer.arm.com/documentation/dui0801/g/A64-Floating-point-Instructions/SCVTF--scalar--integer-).
This is possible as the lowest element can be referred to by the
corresponding scalar sub-register with the width of the vector's
constituent elements.

This patch adds new TableGen patterns to remove these redundant
instructions for AArch64, as well as back-end tests to ensure the new
preferred instruction selection result is produced. Existing tests that
relied on the previous selection result have also been updated.



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