[all-commits] [llvm/llvm-project] 871740: [CodeGen] Remove checks for vectors in unsigned di...

[AtariDreams via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 871740761f15df9436fc5e31c0c0ef17b9294891
      https://github.com/llvm/llvm-project/commit/871740761f15df9436fc5e31c0c0ef17b9294891
  Author: AtariDreams <gfunni234 at gmail.com>
  Date:   2024-07-19 (Fri, 19 Jul 2024)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/test/CodeGen/X86/combine-udiv.ll
    M llvm/test/CodeGen/X86/omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll

  Log Message:
  -----------
  [CodeGen] Remove checks for vectors in unsigned division prior to computing leading zeros (#99524)

It turns out we can safely use
DAG.computeKnownBits(N0).countMinLeadingZeros() with constant legal
vectors, so remove the check for it.



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