[all-commits] [llvm/llvm-project] 77ac07: Re-commit "[RISCV] Use Root instead of N throughou...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 77ac07444d32668d5826ef27c24180fb10425213
      https://github.com/llvm/llvm-project/commit/77ac07444d32668d5826ef27c24180fb10425213
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-07-18 (Thu, 18 Jul 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll

  Log Message:
  -----------
  Re-commit "[RISCV] Use Root instead of N throughout the worklist loop in combineBinOp_VLToVWBinOp_VL. (#99416)"

With correct test update.

Original message:

We were only checking that the node from the worklist is a supported
root. We weren't checking the strategy or any of its operands unless it
was the original node. For any other node, we just rechecked the
original node's strategy and operands.

The effect of this is that we don't do all of the transformations at
once. Instead, when there were multiple possible nodes to transform we
would only do them as each node was visited by the main DAG combine
worklist.

The test shows a case where we widened an instruction without removing
all of the uses of the vsext. The sext is shared by one node that shares
another sext node with the root another node that doesn't share anything
with the root.



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