[all-commits] [llvm/llvm-project] 563ae6: [RISCV] Don't expand zero stride vp.strided.load i...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 563ae620958a16423669f00a4219a96cf879b1f7
      https://github.com/llvm/llvm-project/commit/563ae620958a16423669f00a4219a96cf879b1f7
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-07-16 (Tue, 16 Jul 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
    M llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll

  Log Message:
  -----------
  [RISCV] Don't expand zero stride vp.strided.load if SEW>XLEN (#98924)

A splat of a <n x i64> on RV32 will get lowered as a zero strided load
anyway (and won't match any .vx splat patterns), so don't expand it to a
scalar load + splat to avoid writing it to the stack.



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