[all-commits] [llvm/llvm-project] a8687d: [compiler-rt][nsan] Improve nsan reports (#98798)
Fangrui Song via All-commits
all-commits at lists.llvm.org
Mon Jul 15 11:12:30 PDT 2024
Branch: refs/heads/users/MaskRay/spr/codegen-set-attributes-on-resolvers-emitted-after-ifuncs
Home: https://github.com/llvm/llvm-project
Commit: a8687dd0262349147ce8ae4d0232a067996be69f
https://github.com/llvm/llvm-project/commit/a8687dd0262349147ce8ae4d0232a067996be69f
Author: Dmitriy Chestnykh <dm.chestnykh at gmail.com>
Date: 2024-07-14 (Sun, 14 Jul 2024)
Changed paths:
M compiler-rt/lib/nsan/nsan.cpp
Log Message:
-----------
[compiler-rt][nsan] Improve nsan reports (#98798)
Currently NSAN prints reports that are entirely red and the terminal
prompt after the program exits is red too. With this change we make red
only `WARNING` summary and the rest of the report isn't colored.
This behavior is similar to the behavior of other sanitizers.
Commit: ba3dcec16b6bb955f2c65a3df157744069441d7f
https://github.com/llvm/llvm-project/commit/ba3dcec16b6bb955f2c65a3df157744069441d7f
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-07-14 (Sun, 14 Jul 2024)
Changed paths:
M clang/lib/AST/Interp/Interp.cpp
Log Message:
-----------
Revert "[clang][Interp] Fix a build failure on Windows"
This reverts commit 27f5c00c607e08b3cdf37f3bf9f4ccf156de2ab4.
Commit: 48d703e7f56282ce5d690e45a129a4a7fd040ee6
https://github.com/llvm/llvm-project/commit/48d703e7f56282ce5d690e45a129a4a7fd040ee6
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-07-14 (Sun, 14 Jul 2024)
Changed paths:
M clang/lib/AST/CMakeLists.txt
M clang/lib/AST/Interp/Compiler.cpp
M clang/lib/AST/Interp/Compiler.h
R clang/lib/AST/Interp/DynamicAllocator.cpp
R clang/lib/AST/Interp/DynamicAllocator.h
M clang/lib/AST/Interp/EvalEmitter.cpp
M clang/lib/AST/Interp/EvaluationResult.cpp
M clang/lib/AST/Interp/EvaluationResult.h
M clang/lib/AST/Interp/Interp.cpp
M clang/lib/AST/Interp/Interp.h
M clang/lib/AST/Interp/InterpBlock.h
M clang/lib/AST/Interp/InterpState.cpp
M clang/lib/AST/Interp/InterpState.h
M clang/lib/AST/Interp/Opcodes.td
M clang/lib/AST/Interp/Pointer.h
R clang/test/AST/Interp/new-delete.cpp
M clang/test/Rewriter/rewrite-modern-catch.m
M clang/test/SemaCXX/delete.cpp
M clang/test/SemaCXX/new-delete.cpp
Log Message:
-----------
Revert "[clang][Interp] Implement dynamic memory allocation handling (#70306)"
This reverts commit fa133d3151b5e428b1c5819d29b0ad28a90882a2.
It looks like this has some more serious problems:
https://lab.llvm.org/buildbot/#/builders/39/builds/528
As well as build failures on MacOS.
Commit: efde640cdfede834fa79e0eea69f82fb769d6beb
https://github.com/llvm/llvm-project/commit/efde640cdfede834fa79e0eea69f82fb769d6beb
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-07-14 (Sun, 14 Jul 2024)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/AST/BUILD.gn
Log Message:
-----------
[gn build] Port 48d703e7f562
Commit: fc9cd3272b50f4ee9f18c4ab82c278bbb014d99f
https://github.com/llvm/llvm-project/commit/fc9cd3272b50f4ee9f18c4ab82c278bbb014d99f
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-07-14 (Sun, 14 Jul 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/sve-live-out-pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/X86/ephemeral-recipes.ll
A llvm/test/Transforms/LoopVectorize/X86/iv-live-outs.ll
M llvm/test/Transforms/LoopVectorize/iv_outside_user.ll
M llvm/test/Transforms/LoopVectorize/no-fold-tail-by-masking-iv-external-uses.ll
M llvm/test/Transforms/LoopVectorize/pr58811-scev-expansion.ll
M llvm/test/Transforms/LoopVectorize/pr59319-loop-access-info-invalidation.ll
Log Message:
-----------
[VPlan] Don't add live-outs for IV phis.
Resume and exit values for inductions are currently still created
outside of VPlan and independent of the induction recipes. Don't add
live-outs for now, as the additional unneeded users can pessimize other
anlysis.
Fixes https://github.com/llvm/llvm-project/issues/98660.
Commit: 00895efa61f8edaa9a70cb8632ec343bbbe890f7
https://github.com/llvm/llvm-project/commit/00895efa61f8edaa9a70cb8632ec343bbbe890f7
Author: Petr Hosek <phosek at google.com>
Date: 2024-07-14 (Sun, 14 Jul 2024)
Changed paths:
M libc/src/__support/OSUtil/baremetal/io.cpp
M libc/src/__support/OSUtil/baremetal/io.h
Log Message:
-----------
[libc] Extend the baremetal I/O vendor ABI (#98683)
This refines and extends the external ABI for I/O, later changes will
update the baremetal implementations of I/O functions to use these.
Commit: 35bb9f158b57a8cccc24bc30d793b176e3219985
https://github.com/llvm/llvm-project/commit/35bb9f158b57a8cccc24bc30d793b176e3219985
Author: Piotr Fusik <piotr at fusion-lang.org>
Date: 2024-07-14 (Sun, 14 Jul 2024)
Changed paths:
M llvm/utils/TableGen/DecoderEmitter.cpp
Log Message:
-----------
[TableGen][NFC] Use `decodeULEB128AndIncUnsafe` in `decodeInstruction` (#98619)
Commit: 7c15fbae31ab065a370a4f90a5f5b0d51cb11cf8
https://github.com/llvm/llvm-project/commit/7c15fbae31ab065a370a4f90a5f5b0d51cb11cf8
Author: Kazu Hirata <kazu at google.com>
Date: 2024-07-14 (Sun, 14 Jul 2024)
Changed paths:
M llvm/lib/Linker/IRMover.cpp
Log Message:
-----------
[Linker] Use a range-based for loop (NFC) (#98785)
Commit: 73acf8d755e04996f17b7694b4794459e492dede
https://github.com/llvm/llvm-project/commit/73acf8d755e04996f17b7694b4794459e492dede
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-07-14 (Sun, 14 Jul 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Driver/Options.td
M clang/lib/Basic/Targets/RISCV.cpp
M clang/lib/Basic/Targets/RISCV.h
M clang/lib/Driver/ToolChains/Arch/RISCV.cpp
M clang/test/Driver/riscv-features.c
M llvm/include/llvm/TargetParser/RISCVTargetParser.h
M llvm/lib/TargetParser/RISCVTargetParser.cpp
M llvm/test/TableGen/riscv-target-def.td
M llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
Log Message:
-----------
[RISCV] Add -m[no-]scalar-strict-align and -m[no-]vector-strict-align. (#95024)
Commit: ca4ebae38c09b48c78789b77e7a98ec149957716
https://github.com/llvm/llvm-project/commit/ca4ebae38c09b48c78789b77e7a98ec149957716
Author: Piotr Fusik <p.fusik at samsung.com>
Date: 2024-07-14 (Sun, 14 Jul 2024)
Changed paths:
M clang/lib/CodeGen/CGExpr.cpp
Log Message:
-----------
[clang][NFC] Fix a warning (#98611)
enumerated and non-enumerated type in conditional expression
Commit: 2f55e551011d4ff2227be35bf8b64516d8dcb700
https://github.com/llvm/llvm-project/commit/2f55e551011d4ff2227be35bf8b64516d8dcb700
Author: Kazu Hirata <kazu at google.com>
Date: 2024-07-14 (Sun, 14 Jul 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
M llvm/lib/Transforms/Scalar/Reassociate.cpp
M llvm/lib/Transforms/Utils/InlineFunction.cpp
Log Message:
-----------
[Transforms] Use range-based for loops (NFC) (#98725)
Commit: 6ffa995517a9b4c15aba0eb511cba309e21808cf
https://github.com/llvm/llvm-project/commit/6ffa995517a9b4c15aba0eb511cba309e21808cf
Author: Petr Hosek <phosek at google.com>
Date: 2024-07-14 (Sun, 14 Jul 2024)
Changed paths:
M clang/cmake/caches/Fuchsia-stage2.cmake
Log Message:
-----------
[Fuchsia][CMake] Use MinSizeRel for baremetal runtimes (#98835)
Size matters more than performance for these targets.
Commit: 0fc4e3052454391b7e54a05c1918527cf36c74cc
https://github.com/llvm/llvm-project/commit/0fc4e3052454391b7e54a05c1918527cf36c74cc
Author: Rainer Orth <ro at gcc.gnu.org>
Date: 2024-07-14 (Sun, 14 Jul 2024)
Changed paths:
M llvm/lib/Support/Unix/Path.inc
Log Message:
-----------
[Support] Don't use StringRef::equals in Path.inc (#98839)
The removal of StringRef::equals in
3fa409f2318ef790cc44836afe9a72830715ad84 broke the
[Solaris/sparcv9](https://lab.llvm.org/buildbot/#/builders/13/builds/724)
and
[Solaris/amd64](https://lab.llvm.org/staging/#/builders/94/builds/5176)
buildbots:
```
In file included from /vol/llvm/src/llvm-project/git/llvm/lib/Support/Path.cpp:1200:
/vol/llvm/src/llvm-project/git/llvm/lib/Support/Unix/Path.inc:519:18: error: no member named 'equals' in 'llvm::StringRef'
519 | return !fstype.equals("nfs");
| ~~~~~~ ^
```
Fixed by switching to `operator!=` instead.
Tested on sparcv9-sun-solaris2.11 and amd64-pc-solaris2.11.
Commit: 6441df3b5930ff9f8b3b9af6fd5d2684cf9a337b
https://github.com/llvm/llvm-project/commit/6441df3b5930ff9f8b3b9af6fd5d2684cf9a337b
Author: realqhc <caiqihan021 at hotmail.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsRISCVXCV.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
A llvm/test/CodeGen/RISCV/xcvmac.ll
Log Message:
-----------
[RISCV] Implement Intrinsics for XCVmac Extension in CV32E40P (#83112)
Implement XCVmac intrinsics for CV32E40P according to the specification.
This commit is part of a patch-set to upstream the vendor specific
extensions of CV32E40P that need LLVM intrinsics to implement Clang
builtins.
Contributors: @CharKeaney, @ChunyuLiao, @jeremybennett, @lewis-revill,
@NandniJamnadas, @PaoloS02, @serkm, @simonpcook, @xingmingjie.
Commit: d83d09facdc37bd1bd8c697e16d889ff8a4f369b
https://github.com/llvm/llvm-project/commit/d83d09facdc37bd1bd8c697e16d889ff8a4f369b
Author: Shan Huang <52285902006 at stu.ecnu.edu.cn>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
A llvm/test/Transforms/LoopStrengthReduce/X86/preserving-debugloc-phi-binop.ll
Log Message:
-----------
[DebugInfo][LoopStrengthReduce] Fix missing debug location updates (#97519)
Fix #97510 .
Note that, for the new phi instruction `NewPH`, which replaces the old
phi `PH` and the cast `ShadowUse`, I choose to propagate the debug
location of `PH` to it, because the cast is eliminated according to the
optimization semantics.
Commit: 33bdb87adc16e2890beeeb64a980317e7c4292d7
https://github.com/llvm/llvm-project/commit/33bdb87adc16e2890beeeb64a980317e7c4292d7
Author: Shan Huang <52285902006 at stu.ecnu.edu.cn>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp
A llvm/test/Transforms/SimpleLoopUnswitch/preserving-dropping-debugloc-nontrivial.ll
Log Message:
-----------
[DebugInfo][SimpleLoopUnswitch] Fix missing debug location updates (#97662)
Fix #97559 .
For the change at line 1253, I propagate the debug location of the
terminator (i.e., the insertion point) to the new phi. because `MergeBB`
is generated by splitting `ExitBB` several lines above, it only has the
terminator, which could provide a reasonable debug location.
For the change at line 2348, I switch the order of moving and cloning
`TI`. Because `NewTI` cloned from `TI` is inserted into the original
place where `TI` is, `NewTI` should preserve the origianl debug
location. At the same time, doing this allows us to propagate the debug
location to the new branch instruction replacing `NewTI` (the change at
line 2446).
Commit: adaff46d087799072438dd744b038e6fd50a2d78
https://github.com/llvm/llvm-project/commit/adaff46d087799072438dd744b038e6fd50a2d78
Author: dyung <douglas.yung at sony.com>
Date: 2024-07-14 (Sun, 14 Jul 2024)
Changed paths:
M clang/test/CodeGenHIP/default-attributes.hip
M llvm/docs/ReleaseNotes.rst
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp-atomics-gfx940.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/implicit-kernarg-backend-usage-global-isel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement-stack-lower.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.large.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel-system-sgprs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fence.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.shared.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.kernarg.segment.ptr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.queue.ptr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sbfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workgroup.id.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/memory-legalizer-atomic-fence.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll
M llvm/test/CodeGen/AMDGPU/add.ll
M llvm/test/CodeGen/AMDGPU/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/agpr-register-count.ll
M llvm/test/CodeGen/AMDGPU/always-uniform.ll
M llvm/test/CodeGen/AMDGPU/amd.endpgm.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-sincos.ll
M llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll
M llvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll
M llvm/test/CodeGen/AMDGPU/amdpal-elf.ll
M llvm/test/CodeGen/AMDGPU/anyext.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomics_cond_sub.ll
M llvm/test/CodeGen/AMDGPU/attr-amdgpu-waves-per-eu.ll
M llvm/test/CodeGen/AMDGPU/attributor-noopt.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/bfe-combine.ll
M llvm/test/CodeGen/AMDGPU/bfe-patterns.ll
M llvm/test/CodeGen/AMDGPU/bfi_int.ll
M llvm/test/CodeGen/AMDGPU/bfi_nested.ll
M llvm/test/CodeGen/AMDGPU/bfm.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/br_cc.f16.ll
M llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
M llvm/test/CodeGen/AMDGPU/bswap.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll
M llvm/test/CodeGen/AMDGPU/build_vector.ll
M llvm/test/CodeGen/AMDGPU/call-constexpr.ll
M llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll
M llvm/test/CodeGen/AMDGPU/call-reqd-group-size.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs-packed.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/cc-update.ll
M llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx1030.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx908.ll
M llvm/test/CodeGen/AMDGPU/cgp-bitfield-extract.ll
M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
M llvm/test/CodeGen/AMDGPU/clamp-modifier.ll
M llvm/test/CodeGen/AMDGPU/clamp.ll
M llvm/test/CodeGen/AMDGPU/cluster_stores.ll
M llvm/test/CodeGen/AMDGPU/coalesce-vgpr-alignment.ll
M llvm/test/CodeGen/AMDGPU/code-object-v3.ll
M llvm/test/CodeGen/AMDGPU/codegen-internal-only-func.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/combine-cond-add-sub.ll
M llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll
M llvm/test/CodeGen/AMDGPU/combine-vload-extract.ll
M llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
M llvm/test/CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll
M llvm/test/CodeGen/AMDGPU/copy_to_scc.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/ctpop16.ll
M llvm/test/CodeGen/AMDGPU/ctpop64.ll
M llvm/test/CodeGen/AMDGPU/cttz.ll
M llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dag-divergence-atomic.ll
M llvm/test/CodeGen/AMDGPU/dagcomb-extract-vec-elt-different-sizes.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-sext-inreg.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll
M llvm/test/CodeGen/AMDGPU/ds-alignment.ll
M llvm/test/CodeGen/AMDGPU/ds-combine-large-stride.ll
M llvm/test/CodeGen/AMDGPU/ds-combine-with-dependence.ll
M llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
M llvm/test/CodeGen/AMDGPU/ds_read2.ll
M llvm/test/CodeGen/AMDGPU/ds_write2.ll
M llvm/test/CodeGen/AMDGPU/early-inline.ll
M llvm/test/CodeGen/AMDGPU/elf-notes.ll
M llvm/test/CodeGen/AMDGPU/exec-mask-opt-cannot-create-empty-or-backward-segment.ll
M llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i16.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll
M llvm/test/CodeGen/AMDGPU/extractelt-to-trunc.ll
M llvm/test/CodeGen/AMDGPU/fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fabs.ll
M llvm/test/CodeGen/AMDGPU/fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f32.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.ll
M llvm/test/CodeGen/AMDGPU/fdiv32-to-rcp-folding.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/fma-combine.ll
M llvm/test/CodeGen/AMDGPU/fma.ll
M llvm/test/CodeGen/AMDGPU/fmax3.ll
M llvm/test/CodeGen/AMDGPU/fmax_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fmin3.ll
M llvm/test/CodeGen/AMDGPU/fmin_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
M llvm/test/CodeGen/AMDGPU/fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fneg.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg.ll
M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx1200.ll
M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx940.ll
M llvm/test/CodeGen/AMDGPU/fp-classify.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp32.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp64.ll
M llvm/test/CodeGen/AMDGPU/fp32_to_fp16.ll
M llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
M llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
M llvm/test/CodeGen/AMDGPU/fpext.f16.ll
M llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
M llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/fshl.ll
M llvm/test/CodeGen/AMDGPU/fshr.ll
M llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll
M llvm/test/CodeGen/AMDGPU/fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/fused-bitlogic.ll
M llvm/test/CodeGen/AMDGPU/gds-allocation.ll
M llvm/test/CodeGen/AMDGPU/gep-const-address-space.ll
M llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomics-fp-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/global-constant.ll
M llvm/test/CodeGen/AMDGPU/global-i16-load-store.ll
M llvm/test/CodeGen/AMDGPU/global-load-saddr-to-vaddr.ll
M llvm/test/CodeGen/AMDGPU/global_atomics.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/global_smrd.ll
M llvm/test/CodeGen/AMDGPU/half.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-agpr-register-count.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-heap-v5.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-hostcall-v4.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-hostcall-v5.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-kernel-code-props.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-multigrid-sync-arg-v5.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-queue-ptr-v5.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-queueptr-v5.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-resource-usage-function-ordering.ll
M llvm/test/CodeGen/AMDGPU/hsa.ll
M llvm/test/CodeGen/AMDGPU/idiv-licm.ll
M llvm/test/CodeGen/AMDGPU/idot2.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/idot8s.ll
M llvm/test/CodeGen/AMDGPU/idot8u.ll
M llvm/test/CodeGen/AMDGPU/imm.ll
M llvm/test/CodeGen/AMDGPU/imm16.ll
M llvm/test/CodeGen/AMDGPU/immv216.ll
M llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll
M llvm/test/CodeGen/AMDGPU/implicitarg-attributes.ll
M llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll
M llvm/test/CodeGen/AMDGPU/infinite-loop.ll
M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
M llvm/test/CodeGen/AMDGPU/inline-attr.ll
M llvm/test/CodeGen/AMDGPU/inlineasm-packed.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
M llvm/test/CodeGen/AMDGPU/ipra.ll
M llvm/test/CodeGen/AMDGPU/kernarg-size.ll
M llvm/test/CodeGen/AMDGPU/kernel-args.ll
M llvm/test/CodeGen/AMDGPU/kernel-argument-dag-lowering.ll
M llvm/test/CodeGen/AMDGPU/kill-infinite-loop.ll
M llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll
M llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll
M llvm/test/CodeGen/AMDGPU/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.cond.sub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier-fastregalloc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.row.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f16.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmul.legacy.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.atomic.ordered.add.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.kernel.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.queue.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.wait.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sleep.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx11.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx12.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.floor.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.get.fpmode.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
M llvm/test/CodeGen/AMDGPU/llvm.r600.read.local.size.ll
M llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.ll
M llvm/test/CodeGen/AMDGPU/llvm.set.rounding.ll
M llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
M llvm/test/CodeGen/AMDGPU/local-64.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-memory.amdgcn.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
M llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
M llvm/test/CodeGen/AMDGPU/loop_break.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-memcpy.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-hybrid.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/lshl64-to-32.ll
M llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll
M llvm/test/CodeGen/AMDGPU/mad.u16.ll
M llvm/test/CodeGen/AMDGPU/mad24-get-global-id.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
M llvm/test/CodeGen/AMDGPU/madak.ll
M llvm/test/CodeGen/AMDGPU/match-perm-extract-vector-elt-bug.ll
M llvm/test/CodeGen/AMDGPU/max-hard-clause-length.ll
M llvm/test/CodeGen/AMDGPU/max.i16.ll
M llvm/test/CodeGen/AMDGPU/max.ll
M llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
M llvm/test/CodeGen/AMDGPU/memcpy-scalar-load.ll
M llvm/test/CodeGen/AMDGPU/memmove-scalar-load.ll
M llvm/test/CodeGen/AMDGPU/memory_clause.ll
M llvm/test/CodeGen/AMDGPU/mfma-bf16-vgpr-cd-select.ll
M llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll
M llvm/test/CodeGen/AMDGPU/mfma-vgpr-cd-select-gfx940.ll
M llvm/test/CodeGen/AMDGPU/mfma-vgpr-cd-select.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw-system.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans.ll
M llvm/test/CodeGen/AMDGPU/mubuf-offset-private.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
M llvm/test/CodeGen/AMDGPU/mul_int24.ll
M llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
M llvm/test/CodeGen/AMDGPU/multilevel-break.ll
M llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll
M llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
M llvm/test/CodeGen/AMDGPU/omod.ll
M llvm/test/CodeGen/AMDGPU/optimize-compare.ll
M llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
M llvm/test/CodeGen/AMDGPU/or.ll
M llvm/test/CodeGen/AMDGPU/pack.v2f16.ll
M llvm/test/CodeGen/AMDGPU/pack.v2i16.ll
M llvm/test/CodeGen/AMDGPU/packed-op-sel.ll
M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
M llvm/test/CodeGen/AMDGPU/partial-shift-shrink.ll
M llvm/test/CodeGen/AMDGPU/permlane-op-sel.ll
M llvm/test/CodeGen/AMDGPU/permlane16_opsel.ll
M llvm/test/CodeGen/AMDGPU/permute.ll
M llvm/test/CodeGen/AMDGPU/permute_i8.ll
M llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll
M llvm/test/CodeGen/AMDGPU/preload-kernarg-header.ll
M llvm/test/CodeGen/AMDGPU/preload-kernargs.ll
M llvm/test/CodeGen/AMDGPU/private-memory-atomics.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/ptr-buffer-alias-scheduling.ll
M llvm/test/CodeGen/AMDGPU/rcp-pattern.ll
M llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-extended-image-insts.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-functions.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-gws.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-s-time.ll
M llvm/test/CodeGen/AMDGPU/rotl.ll
M llvm/test/CodeGen/AMDGPU/rotr.ll
M llvm/test/CodeGen/AMDGPU/rsq.f32.ll
M llvm/test/CodeGen/AMDGPU/s_addk_i32.ll
M llvm/test/CodeGen/AMDGPU/sad.ll
M llvm/test/CodeGen/AMDGPU/saddo.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.v8i16.ll
M llvm/test/CodeGen/AMDGPU/scc-clobbered-sgpr-to-vmem-spill.ll
M llvm/test/CodeGen/AMDGPU/sdiv.ll
M llvm/test/CodeGen/AMDGPU/sdiv64.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/AMDGPU/select-constant-cttz.ll
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/setcc.ll
M llvm/test/CodeGen/AMDGPU/sext-divergence-driven-isel.ll
M llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
M llvm/test/CodeGen/AMDGPU/sgpr-copy-local-cse.ll
M llvm/test/CodeGen/AMDGPU/shift-and-i128-ubfe.ll
M llvm/test/CodeGen/AMDGPU/shift-and-i64-ubfe.ll
M llvm/test/CodeGen/AMDGPU/shift-i128.ll
M llvm/test/CodeGen/AMDGPU/shl.ll
M llvm/test/CodeGen/AMDGPU/shl.v2i16.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cfg-loop-assert.ll
M llvm/test/CodeGen/AMDGPU/si-unify-exit-multiple-unreachables.ll
M llvm/test/CodeGen/AMDGPU/sibling-call.ll
M llvm/test/CodeGen/AMDGPU/sign_extend.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/simplify-libcalls.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/sitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/smfmac_no_agprs.ll
M llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
M llvm/test/CodeGen/AMDGPU/sopk-compares.ll
M llvm/test/CodeGen/AMDGPU/spill-agpr.ll
M llvm/test/CodeGen/AMDGPU/spill-offset-calculation.ll
M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
M llvm/test/CodeGen/AMDGPU/spill-sgpr-stack-no-sgpr.ll
M llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
M llvm/test/CodeGen/AMDGPU/spill-writelane-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sra.ll
M llvm/test/CodeGen/AMDGPU/srem.ll
M llvm/test/CodeGen/AMDGPU/srem64.ll
M llvm/test/CodeGen/AMDGPU/srl.ll
M llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
M llvm/test/CodeGen/AMDGPU/stack-realign-kernel.ll
M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
M llvm/test/CodeGen/AMDGPU/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll
M llvm/test/CodeGen/AMDGPU/tid-kd-xnack-any.ll
M llvm/test/CodeGen/AMDGPU/tid-kd-xnack-off.ll
M llvm/test/CodeGen/AMDGPU/tid-kd-xnack-on.ll
M llvm/test/CodeGen/AMDGPU/trap-abis.ll
M llvm/test/CodeGen/AMDGPU/trap.ll
M llvm/test/CodeGen/AMDGPU/trunc-combine.ll
M llvm/test/CodeGen/AMDGPU/trunc-store.ll
M llvm/test/CodeGen/AMDGPU/trunc.ll
M llvm/test/CodeGen/AMDGPU/uaddo.ll
M llvm/test/CodeGen/AMDGPU/udiv.ll
M llvm/test/CodeGen/AMDGPU/udiv64.ll
M llvm/test/CodeGen/AMDGPU/udivrem.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/uitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/uniform-cfg.ll
M llvm/test/CodeGen/AMDGPU/uniform-select.ll
M llvm/test/CodeGen/AMDGPU/urem64.ll
M llvm/test/CodeGen/AMDGPU/usubo.ll
M llvm/test/CodeGen/AMDGPU/v_add_u64_pseudo_sdwa.ll
M llvm/test/CodeGen/AMDGPU/v_cmp_gfx11.ll
M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
M llvm/test/CodeGen/AMDGPU/v_madak_f16.ll
M llvm/test/CodeGen/AMDGPU/v_pack.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/AMDGPU/v_sub_u64_pseudo_sdwa.ll
M llvm/test/CodeGen/AMDGPU/vector-extract-insert.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/waterfall_kills_scc.ll
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
M llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
M llvm/test/CodeGen/AMDGPU/xor.ll
M llvm/test/CodeGen/AMDGPU/zext-divergence-driven-isel.ll
M llvm/test/CodeGen/MIR/AMDGPU/long-branch-reg-all-sgpr-used.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/flat_atomic.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
Log Message:
-----------
Revert "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
This reverts commits 677cc15e0ff2e0e6aa30538eb187990a6a8f53c0 and
78bc1b64a6dc3fb6191355a5e1b502be8b3668e7.
The test CodeGenHIP/default-attributes.hip is failing on multiple bots
even after the attempted fix including the following:
- https://lab.llvm.org/buildbot/#/builders/3/builds/1473
- https://lab.llvm.org/buildbot/#/builders/65/builds/1380
- https://lab.llvm.org/buildbot/#/builders/161/builds/595
- https://lab.llvm.org/buildbot/#/builders/154/builds/1372
- https://lab.llvm.org/buildbot/#/builders/133/builds/1547
- https://lab.llvm.org/buildbot/#/builders/81/builds/755
- https://lab.llvm.org/buildbot/#/builders/40/builds/570
- https://lab.llvm.org/buildbot/#/builders/13/builds/748
- https://lab.llvm.org/buildbot/#/builders/12/builds/1845
- https://lab.llvm.org/buildbot/#/builders/11/builds/1695
- https://lab.llvm.org/buildbot/#/builders/190/builds/1829
- https://lab.llvm.org/buildbot/#/builders/193/builds/962
- https://lab.llvm.org/buildbot/#/builders/23/builds/991
- https://lab.llvm.org/buildbot/#/builders/144/builds/2256
- https://lab.llvm.org/buildbot/#/builders/46/builds/1614
These bots have been broken for a day, so reverting to get everything
back to green.
Commit: 4ca024c877e3eb20c0af518d3335883fb7b4b910
https://github.com/llvm/llvm-project/commit/4ca024c877e3eb20c0af518d3335883fb7b4b910
Author: Oleksandr T <oleksandr.tarasiuk at outlook.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/test/CXX/class/class.compare/class.compare.default/p1.cpp
Log Message:
-----------
[Clang] Fix cast failures by adjusting the resolution of record declaration contexts to handle semantic and lexical distinctions (#96228)
Fixes #96043
Commit: 5c8eb83ce8e4ef40fbd61a05f1de6394eb908da4
https://github.com/llvm/llvm-project/commit/5c8eb83ce8e4ef40fbd61a05f1de6394eb908da4
Author: Carl Ritson <carl.ritson at amd.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M llvm/test/CodeGen/AMDGPU/fix-wwm-vgpr-copy.ll
Log Message:
-----------
[AMDGPU] Generate test fix-wwm-vgpr-copy.ll (NFC)
Commit: 8da3852f44c64ac4535128741695b9e9d8ee27ef
https://github.com/llvm/llvm-project/commit/8da3852f44c64ac4535128741695b9e9d8ee27ef
Author: Carl Ritson <carl.ritson at amd.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M llvm/test/CodeGen/AMDGPU/fix-wwm-vgpr-copy.ll
Log Message:
-----------
Revert "[AMDGPU] Generate test fix-wwm-vgpr-copy.ll (NFC)"
This reverts commit 5c8eb83ce8e4ef40fbd61a05f1de6394eb908da4.
Commit: e025e5ef44b736b48b8a2ee230a11f674b734b32
https://github.com/llvm/llvm-project/commit/e025e5ef44b736b48b8a2ee230a11f674b734b32
Author: Carl Ritson <carl.ritson at amd.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M llvm/test/CodeGen/AMDGPU/fix-wwm-vgpr-copy.ll
Log Message:
-----------
[AMDGPU] Reland generated test fix-wwm-vgpr-copy.ll (NFC)
Fix issues left over after generation.
Commit: c09ed6a29e392e406623f7c4dc0a8240d2cbc9f2
https://github.com/llvm/llvm-project/commit/c09ed6a29e392e406623f7c4dc0a8240d2cbc9f2
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
A llvm/include/llvm/CodeGen/MachineVerifier.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/include/llvm/Passes/StandardInstrumentations.h
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/StandardInstrumentations.cpp
M llvm/test/CodeGen/AMDGPU/verifier-sdwa-cvt.mir
M llvm/test/CodeGen/AMDGPU/verify-constant-bus-violations.mir
M llvm/test/CodeGen/AMDGPU/verify-ds-gws-align.mir
M llvm/test/CodeGen/AMDGPU/verify-duplicate-literal.mir
M llvm/test/CodeGen/AMDGPU/verify-gfx90a-aligned-vgprs.mir
M llvm/test/CodeGen/AMDGPU/verify-image-vaddr-align.mir
M llvm/test/CodeGen/AMDGPU/verify-image.mir
M llvm/test/CodeGen/AMDGPU/verify-scalar-store.mir
M llvm/test/CodeGen/AMDGPU/verify-sop.mir
M llvm/test/CodeGen/AMDGPU/verify-vimage-vsample.mir
M llvm/test/CodeGen/AMDGPU/verify-vopd-gfx12.mir
M llvm/test/CodeGen/AMDGPU/verify-vopd.mir
M llvm/test/CodeGen/MIR/Generic/dbg-value-missing-loc.mir
M llvm/test/CodeGen/MIR/X86/dbg-value-list.mir
M llvm/test/CodeGen/RISCV/verify-instr.mir
M llvm/tools/llc/NewPMDriver.cpp
Log Message:
-----------
[CodeGen][NewPM] Port `MachineVerifier` to new pass manager (#98628)
- Add `MachineVerifierPass`.
- Use complete `MachineVerifierPass` in `VerifyInstrumentation` if
possible.
`LiveStacksAnalysis` will be added in future, all other analyses are
done.
Commit: 36984536be147ce4f53d7b05a77c8ccc79227271
https://github.com/llvm/llvm-project/commit/36984536be147ce4f53d7b05a77c8ccc79227271
Author: Carl Ritson <carl.ritson at amd.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
Log Message:
-----------
[AMDGPU] SIWholeQuadMode: remove unnecessary map access (NFCI)
Commit: 662c6fc74c1ae7fdefd27524dfaeb7f3e9a1f553
https://github.com/llvm/llvm-project/commit/662c6fc74c1ae7fdefd27524dfaeb7f3e9a1f553
Author: donald chen <chenxunyu1993 at gmail.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M mlir/include/mlir/Dialect/Bufferization/Transforms/Passes.h
M mlir/lib/Conversion/BufferizationToMemRef/BufferizationToMemRef.cpp
M mlir/lib/Dialect/Bufferization/Transforms/LowerDeallocations.cpp
M mlir/test/Dialect/Bufferization/Transforms/lower-deallocations.mlir
Log Message:
-----------
[mlir] [bufferize] fix bufferize deallocation error in nest symbol table (#98476)
In nested symbols, the dealloc_helper function generated by lower
deallocations pass was incorrectly positioned, causing calls fail. This
patch fixes this issue.
Commit: 34bfed63313d1340378fc1be931253333db8c36c
https://github.com/llvm/llvm-project/commit/34bfed63313d1340378fc1be931253333db8c36c
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/test/Transforms/EarlyCSE/math-2.ll
Log Message:
-----------
[ConstantFold] Fix result type when folding powi.f16 (#98681)
Fixes #98665.
Commit: 557ef043afd04da91e79425133f14c94831a646c
https://github.com/llvm/llvm-project/commit/557ef043afd04da91e79425133f14c94831a646c
Author: Luke Lau <luke at igalia.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
M llvm/test/Transforms/LoopStrengthReduce/RISCV/lsr-drop-solution.ll
Log Message:
-----------
[RISCV] Copy AVLs whose LiveIntervals aren't extendable in insertVSETVLI (#98342)
Currently before forwarding an AVL we do a simple non-exhaustive check
to see if its LiveInterval is extendable. But we also need to check for
this when we're extending an AVL's LiveInterval via merging the
VSETVLIInfos in transferBefore with equally zero AVLs.
Rather than trying to conservatively prevent these cases, this inserts a
copy of the AVL instead if we don't know we'll be able to extend it.
This is likely to be more robust, and even if the extra copy is
undesirable these cases should be rare in practice.
Commit: 37211d17f9f237e8a820ed81c1b5e92c22b45d5e
https://github.com/llvm/llvm-project/commit/37211d17f9f237e8a820ed81c1b5e92c22b45d5e
Author: PeterChou1 <peter.chou at mail.utoronto.ca>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M clang-tools-extra/test/clang-doc/basic-project.test
Log Message:
-----------
[clang-doc] Support markdown and simplify checks (#97684)
This patch modifies the basic-project in clang-doc. Currently we're
matching the entire html output. This patch modifies it so that we only
match the parts relevant to the documentation logic instead just
matching the boilerplate code. This patch also adds the markdown output
to the basic-project test
Commit: 587308c3436b3fb757d3ba4343ccd4bd0c90f429
https://github.com/llvm/llvm-project/commit/587308c3436b3fb757d3ba4343ccd4bd0c90f429
Author: Paschalis Mpeis <paschalis.mpeis at arm.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M bolt/include/bolt/Core/MCPlusBuilder.h
M bolt/lib/Target/X86/X86MCPlusBuilder.cpp
A bolt/test/AArch64/dummy-return.s
Log Message:
-----------
[BOLT][AArch64] Provide createDummyReturnFunction (#96626)
AArch64 needs this function when instrumenting statically-linked binaries.
Sample commands:
```bash
clang -Wl,-q test.c -static -o out
llvm-bolt -instrument -instrumentation-sleep-time=5 out -o out.instr
```
Commit: a5a29a26aaf0d7e63101471250d32e9b7230fe73
https://github.com/llvm/llvm-project/commit/a5a29a26aaf0d7e63101471250d32e9b7230fe73
Author: Michael Klemm <michael.klemm at amd.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M flang/docs/Intrinsics.md
M flang/include/flang/Optimizer/Builder/IntrinsicCall.h
M flang/include/flang/Optimizer/Builder/Runtime/Intrinsics.h
M flang/include/flang/Runtime/misc-intrinsic.h
M flang/lib/Evaluate/intrinsics.cpp
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/lib/Optimizer/Builder/Runtime/Intrinsics.cpp
M flang/runtime/misc-intrinsic.cpp
A flang/test/Lower/Intrinsics/rename.f90
M flang/test/Lower/namelist.f90
Log Message:
-----------
[Flang] Implement RENAME intrinsic (code-gen + runtime entry point) (#98359)
This PR implements the RENAME intrinsic, which is a GFortran extension
(see
https://gcc.gnu.org/onlinedocs/gfortran/intrinsic-procedures/rename.html).
Commit: 18c70b070b6dd7cead8f049dde0542dc75ed28fd
https://github.com/llvm/llvm-project/commit/18c70b070b6dd7cead8f049dde0542dc75ed28fd
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M clang/include/clang/Sema/Sema.h
M clang/lib/Sema/CMakeLists.txt
M clang/lib/Sema/SemaTemplate.cpp
A clang/lib/Sema/SemaTemplateDeductionGuide.cpp
Log Message:
-----------
[clang] Refactor: Move CTAD code from SemaTemplate.cpp to a dedicated file, NFC (#98524)
Split out the deduction guide related code from SemaTemplate.cpp to a
dedicated file.
These code has grown significantly, and moving it to a separate file
will improve code organization.
Commit: 5555a9e657939dafb569a825fecd1d0f4202b21d
https://github.com/llvm/llvm-project/commit/5555a9e657939dafb569a825fecd1d0f4202b21d
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/Sema/BUILD.gn
Log Message:
-----------
[gn build] Port 18c70b070b6d
Commit: caa0e42ceb6e671d68b8b8e1d04f136696a4228b
https://github.com/llvm/llvm-project/commit/caa0e42ceb6e671d68b8b8e1d04f136696a4228b
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/test/Transforms/EarlyCSE/math-2.ll
Log Message:
-----------
Fix assertion failure in PR98681 (#98860)
See https://en.cppreference.com/w/cpp/numeric/math/pow:
```
C++98 added overloads where exp has type int on top of C [pow()](https://en.cppreference.com/w/c/numeric/math/pow), and the return type of std::pow(float, int) was float. However, the additional overloads introduced in C++11 specify that std::pow(float, int) should return double. [LWG issue 550](https://cplusplus.github.io/LWG/issue550) was raised to target this conflict, and the resolution is to removed the extra int exp overloads.
```
Commit: 01191874f9011d3ce8b7c2830ece1f030c60da7f
https://github.com/llvm/llvm-project/commit/01191874f9011d3ce8b7c2830ece1f030c60da7f
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
A llvm/include/llvm/CodeGen/TwoAddressInstructionPass.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/test/CodeGen/AArch64/statepoint-twoaddr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/twoaddr-extract-dyn-v7f64.mir
M llvm/test/CodeGen/AMDGPU/early-lis-two-address-partial-def.mir
M llvm/test/CodeGen/AMDGPU/gfx10-twoaddr-fma.mir
M llvm/test/CodeGen/AMDGPU/gfx11-twoaddr-fma.mir
M llvm/test/CodeGen/AMDGPU/twoaddr-fma-f64.mir
M llvm/test/CodeGen/AMDGPU/twoaddr-fma.mir
M llvm/test/CodeGen/AMDGPU/twoaddr-mad.mir
M llvm/test/CodeGen/AMDGPU/twoaddr-wmma.mir
M llvm/test/CodeGen/Hexagon/two-addr-tied-subregs.mir
M llvm/test/CodeGen/X86/distancemap.mir
M llvm/test/CodeGen/X86/statepoint-vreg-twoaddr.mir
M llvm/test/CodeGen/X86/twoaddr-mul2.mir
Log Message:
-----------
[CodeGen] Port `two-address-instructions` to new pass manager (#98632)
Add `TwoAddressInstructionPass`.
Commit: 0d7403184d3b20d16104a36cf78457ddce2af9ba
https://github.com/llvm/llvm-project/commit/0d7403184d3b20d16104a36cf78457ddce2af9ba
Author: David Green <david.green at arm.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.h
M llvm/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp
Log Message:
-----------
[AArch64] Add a AArch64InstrInfo::isFpOrNEON method for checking physical register call. NFC
Commit: 34433fdceb63cb14b69f847a39f6ce98459f3129
https://github.com/llvm/llvm-project/commit/34433fdceb63cb14b69f847a39f6ce98459f3129
Author: Paschalis Mpeis <paschalis.mpeis at arm.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M bolt/docs/CommandLineArgumentReference.md
M bolt/docs/Heatmaps.md
M bolt/include/bolt/Utils/CommandLineOpts.h
M bolt/lib/Profile/Heatmap.cpp
M bolt/lib/Utils/CommandLineOpts.cpp
Log Message:
-----------
[BOLT] Add -print-mappings option to heatmaps (#97567)
Emit a mapping in the legend between the characters/buckets and the text
sections, using:
```sh
llvm-heatmap-bolt -print-mappings ..
```
Example:
```
Legend:
..
Sections:
a/A : .init 0x00000100-0x00000200
b/B : .plt 0x00000200-0x00000500
c/C : .text 0x00010000-0x000a0000
d/D : .fini 0x000a0000-0x000f0000
..
```
Commit: 297fab1b3075a9dcd65213176add34ad7d744bde
https://github.com/llvm/llvm-project/commit/297fab1b3075a9dcd65213176add34ad7d744bde
Author: WANG Rui <wangrui at loongson.cn>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
A llvm/test/CodeGen/LoongArch/typepromotion-overflow.ll
Log Message:
-----------
[LoongArch] Copy typepromotion-overflow.ll from AArch64. NFC
Commit: 9d34b673c0abea4ee0a3dd4c399314411b02f1cc
https://github.com/llvm/llvm-project/commit/9d34b673c0abea4ee0a3dd4c399314411b02f1cc
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/test/Transforms/InstSimplify/ptrtoint.ll
Log Message:
-----------
[InstSimplify] Fold ptrtoint(ptradd(P,X-ptrtoint(P))) to X (#98649)
This is a special case of the general ptrtoint(gep) to add(ptrtoint)
transform that is particularly profitable, as everything folds away.
Proof: https://alive2.llvm.org/ce/z/fwv8_L
Fixes https://github.com/llvm/llvm-project/issues/86417.
Commit: 9ac2b8965264a7f20a3e07c913b25c375a080c0f
https://github.com/llvm/llvm-project/commit/9ac2b8965264a7f20a3e07c913b25c375a080c0f
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M clang/lib/AST/Interp/Interp.cpp
M clang/test/AST/Interp/literals.cpp
Log Message:
-----------
[clang][Interp] Diagnose volatile reads
Commit: 9ad72df55cb74b29193270c28f6974d2af8e0b71
https://github.com/llvm/llvm-project/commit/9ad72df55cb74b29193270c28f6974d2af8e0b71
Author: Mariya Podchishchaeva <mariya.podchishchaeva at intel.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CGDecl.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGExprConstant.cpp
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/lib/CodeGen/CGRecordLayoutBuilder.cpp
M clang/lib/CodeGen/CGStmt.cpp
M clang/lib/CodeGen/CodeGenFunction.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/CodeGen/CodeGenTypes.cpp
M clang/lib/CodeGen/CodeGenTypes.h
M clang/test/CodeGen/aarch64-byval-temp.c
M clang/test/CodeGen/attr-noundef.cpp
M clang/test/CodeGen/builtins-bitint.c
M clang/test/CodeGen/builtins-elementwise-math.c
M clang/test/CodeGen/builtins-overflow.c
M clang/test/CodeGen/ext-int-cc.c
M clang/test/CodeGen/ext-int-sanitizer.cpp
M clang/test/CodeGen/ext-int.c
M clang/test/CodeGen/extend-arg-64.c
M clang/test/CodeGen/ubsan-shift-bitint.c
M clang/test/CodeGenCXX/ext-int.cpp
M clang/test/CodeGenHIP/printf_nonhostcall.cpp
M clang/test/CodeGenHLSL/builtins/dot-builtin.hlsl
M clang/test/Frontend/fixed_point_comparisons.c
M clang/test/OpenMP/distribute_parallel_for_simd_if_codegen.cpp
M clang/test/OpenMP/parallel_master_taskloop_simd_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_if_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_if_codegen.cpp
M clang/test/OpenMP/target_teams_generic_loop_if_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_if_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_if_codegen.cpp
M clang/test/OpenMP/teams_distribute_simd_codegen.cpp
Log Message:
-----------
[clang] Use different memory layout type for _BitInt(N) in LLVM IR (#91364)
There are two problems with _BitInt prior to this patch:
1. For at least some values of N, we cannot use LLVM's iN for the type
of struct elements, array elements, allocas, global variables, and so
on, because the LLVM layout for that type does not match the high-level
layout of _BitInt(N).
Example: Currently for i128:128 targets correct implementation is
possible either for __int128 or for _BitInt(129+) with lowering to iN,
but not both, since we have now correct implementation of __int128 in
place after a21abc7.
When this happens, opaque [M x i8] types used, where M =
sizeof(_BitInt(N)).
2. LLVM doesn't guarantee any particular extension behavior for integer
types that aren't a multiple of 8. For this reason, all _BitInt types
are now have in-memory representation that is a whole number of bytes.
I.e. for example _BitInt(17) now will have memory layout type i32.
This patch also introduces concept of load/store type and adds an API to
CodeGenTypes that returns the IR type that should be used for load and
store operations. This is particularly useful for the case when a
_BitInt ends up having array of bytes as memory layout type. For
_BitInt(N), let M = sizeof(_BitInt(N)), and let BITS = M * 8. Loads and
stores of iM would both (1) produce far better code from the backends
and (2) be far more optimizable by IR passes than loads and stores of [M
x i8].
Fixes https://github.com/llvm/llvm-project/issues/85139
Fixes https://github.com/llvm/llvm-project/issues/83419
---------
Co-authored-by: John McCall <rjmccall at gmail.com>
Commit: 71051deff27928cff908ea794e09806eee662801
https://github.com/llvm/llvm-project/commit/71051deff27928cff908ea794e09806eee662801
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
M llvm/test/Transforms/MemCpyOpt/memcpy-zero-size.ll
M llvm/test/Transforms/MemCpyOpt/memset-memcpy-dbgloc.ll
M llvm/test/Transforms/MemCpyOpt/memset-memcpy-redundant-memset.ll
M llvm/test/Transforms/MemCpyOpt/opaque-ptr.ll
Log Message:
-----------
[MemCpyOpt] Fix infinite loop in memset+memcpy fold (#98638)
For the case where the memcpy size is zero, this transform is a complex
no-op. This can lead to an infinite loop when the size is zero in a way
that BasicAA understands, because it can still understand that dst and
dst + src_size are MustAlias.
I've tried to mitigate this before using the isZeroSize() check, but we
can hit cases where InstSimplify doesn't understand that the size is
zero, but BasicAA does.
As such, this bites the bullet and adds an explicit isKnownNonZero()
check to guard against no-op transforms.
Fixes https://github.com/llvm/llvm-project/issues/98610.
Commit: b1bcb7ca460fcd317bbc8309e14c8761bf8394e0
https://github.com/llvm/llvm-project/commit/b1bcb7ca460fcd317bbc8309e14c8761bf8394e0
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M clang/test/CodeGenHIP/default-attributes.hip
M llvm/docs/ReleaseNotes.rst
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp-atomics-gfx940.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/implicit-kernarg-backend-usage-global-isel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement-stack-lower.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.large.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel-system-sgprs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fence.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.shared.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.kernarg.segment.ptr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.queue.ptr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sbfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workgroup.id.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/memory-legalizer-atomic-fence.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll
M llvm/test/CodeGen/AMDGPU/add.ll
M llvm/test/CodeGen/AMDGPU/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/agpr-register-count.ll
M llvm/test/CodeGen/AMDGPU/always-uniform.ll
M llvm/test/CodeGen/AMDGPU/amd.endpgm.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-sincos.ll
M llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll
M llvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll
M llvm/test/CodeGen/AMDGPU/amdpal-elf.ll
M llvm/test/CodeGen/AMDGPU/anyext.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomics_cond_sub.ll
M llvm/test/CodeGen/AMDGPU/attr-amdgpu-waves-per-eu.ll
M llvm/test/CodeGen/AMDGPU/attributor-noopt.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/bfe-combine.ll
M llvm/test/CodeGen/AMDGPU/bfe-patterns.ll
M llvm/test/CodeGen/AMDGPU/bfi_int.ll
M llvm/test/CodeGen/AMDGPU/bfi_nested.ll
M llvm/test/CodeGen/AMDGPU/bfm.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/br_cc.f16.ll
M llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
M llvm/test/CodeGen/AMDGPU/bswap.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll
M llvm/test/CodeGen/AMDGPU/build_vector.ll
M llvm/test/CodeGen/AMDGPU/call-constexpr.ll
M llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll
M llvm/test/CodeGen/AMDGPU/call-reqd-group-size.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs-packed.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/cc-update.ll
M llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx1030.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx908.ll
M llvm/test/CodeGen/AMDGPU/cgp-bitfield-extract.ll
M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
M llvm/test/CodeGen/AMDGPU/clamp-modifier.ll
M llvm/test/CodeGen/AMDGPU/clamp.ll
M llvm/test/CodeGen/AMDGPU/cluster_stores.ll
M llvm/test/CodeGen/AMDGPU/coalesce-vgpr-alignment.ll
M llvm/test/CodeGen/AMDGPU/code-object-v3.ll
M llvm/test/CodeGen/AMDGPU/codegen-internal-only-func.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/combine-cond-add-sub.ll
M llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll
M llvm/test/CodeGen/AMDGPU/combine-vload-extract.ll
M llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
M llvm/test/CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll
M llvm/test/CodeGen/AMDGPU/copy_to_scc.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/ctpop16.ll
M llvm/test/CodeGen/AMDGPU/ctpop64.ll
M llvm/test/CodeGen/AMDGPU/cttz.ll
M llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dag-divergence-atomic.ll
M llvm/test/CodeGen/AMDGPU/dagcomb-extract-vec-elt-different-sizes.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-sext-inreg.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll
M llvm/test/CodeGen/AMDGPU/ds-alignment.ll
M llvm/test/CodeGen/AMDGPU/ds-combine-large-stride.ll
M llvm/test/CodeGen/AMDGPU/ds-combine-with-dependence.ll
M llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
M llvm/test/CodeGen/AMDGPU/ds_read2.ll
M llvm/test/CodeGen/AMDGPU/ds_write2.ll
M llvm/test/CodeGen/AMDGPU/early-inline.ll
M llvm/test/CodeGen/AMDGPU/elf-notes.ll
M llvm/test/CodeGen/AMDGPU/exec-mask-opt-cannot-create-empty-or-backward-segment.ll
M llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i16.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll
M llvm/test/CodeGen/AMDGPU/extractelt-to-trunc.ll
M llvm/test/CodeGen/AMDGPU/fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fabs.ll
M llvm/test/CodeGen/AMDGPU/fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f32.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.ll
M llvm/test/CodeGen/AMDGPU/fdiv32-to-rcp-folding.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/fma-combine.ll
M llvm/test/CodeGen/AMDGPU/fma.ll
M llvm/test/CodeGen/AMDGPU/fmax3.ll
M llvm/test/CodeGen/AMDGPU/fmax_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fmin3.ll
M llvm/test/CodeGen/AMDGPU/fmin_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
M llvm/test/CodeGen/AMDGPU/fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fneg.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg.ll
M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx1200.ll
M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx940.ll
M llvm/test/CodeGen/AMDGPU/fp-classify.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp32.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp64.ll
M llvm/test/CodeGen/AMDGPU/fp32_to_fp16.ll
M llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
M llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
M llvm/test/CodeGen/AMDGPU/fpext.f16.ll
M llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
M llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/fshl.ll
M llvm/test/CodeGen/AMDGPU/fshr.ll
M llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll
M llvm/test/CodeGen/AMDGPU/fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/fused-bitlogic.ll
M llvm/test/CodeGen/AMDGPU/gds-allocation.ll
M llvm/test/CodeGen/AMDGPU/gep-const-address-space.ll
M llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomics-fp-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/global-constant.ll
M llvm/test/CodeGen/AMDGPU/global-i16-load-store.ll
M llvm/test/CodeGen/AMDGPU/global-load-saddr-to-vaddr.ll
M llvm/test/CodeGen/AMDGPU/global_atomics.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/global_smrd.ll
M llvm/test/CodeGen/AMDGPU/half.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-agpr-register-count.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-heap-v5.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-hostcall-v4.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-hostcall-v5.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-kernel-code-props.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-multigrid-sync-arg-v5.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-queue-ptr-v5.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-queueptr-v5.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-resource-usage-function-ordering.ll
M llvm/test/CodeGen/AMDGPU/hsa.ll
M llvm/test/CodeGen/AMDGPU/idiv-licm.ll
M llvm/test/CodeGen/AMDGPU/idot2.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/idot8s.ll
M llvm/test/CodeGen/AMDGPU/idot8u.ll
M llvm/test/CodeGen/AMDGPU/imm.ll
M llvm/test/CodeGen/AMDGPU/imm16.ll
M llvm/test/CodeGen/AMDGPU/immv216.ll
M llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll
M llvm/test/CodeGen/AMDGPU/implicitarg-attributes.ll
M llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll
M llvm/test/CodeGen/AMDGPU/infinite-loop.ll
M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
M llvm/test/CodeGen/AMDGPU/inline-attr.ll
M llvm/test/CodeGen/AMDGPU/inlineasm-packed.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
M llvm/test/CodeGen/AMDGPU/ipra.ll
M llvm/test/CodeGen/AMDGPU/kernarg-size.ll
M llvm/test/CodeGen/AMDGPU/kernel-args.ll
M llvm/test/CodeGen/AMDGPU/kernel-argument-dag-lowering.ll
M llvm/test/CodeGen/AMDGPU/kill-infinite-loop.ll
M llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll
M llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll
M llvm/test/CodeGen/AMDGPU/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.cond.sub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier-fastregalloc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.row.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f16.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmul.legacy.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.atomic.ordered.add.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.kernel.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.queue.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.wait.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sleep.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx11.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx12.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.floor.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.get.fpmode.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
M llvm/test/CodeGen/AMDGPU/llvm.r600.read.local.size.ll
M llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.ll
M llvm/test/CodeGen/AMDGPU/llvm.set.rounding.ll
M llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
M llvm/test/CodeGen/AMDGPU/local-64.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-memory.amdgcn.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
M llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
M llvm/test/CodeGen/AMDGPU/loop_break.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-memcpy.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-hybrid.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/lshl64-to-32.ll
M llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll
M llvm/test/CodeGen/AMDGPU/mad.u16.ll
M llvm/test/CodeGen/AMDGPU/mad24-get-global-id.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
M llvm/test/CodeGen/AMDGPU/madak.ll
M llvm/test/CodeGen/AMDGPU/match-perm-extract-vector-elt-bug.ll
M llvm/test/CodeGen/AMDGPU/max-hard-clause-length.ll
M llvm/test/CodeGen/AMDGPU/max.i16.ll
M llvm/test/CodeGen/AMDGPU/max.ll
M llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
M llvm/test/CodeGen/AMDGPU/memcpy-scalar-load.ll
M llvm/test/CodeGen/AMDGPU/memmove-scalar-load.ll
M llvm/test/CodeGen/AMDGPU/memory_clause.ll
M llvm/test/CodeGen/AMDGPU/mfma-bf16-vgpr-cd-select.ll
M llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll
M llvm/test/CodeGen/AMDGPU/mfma-vgpr-cd-select-gfx940.ll
M llvm/test/CodeGen/AMDGPU/mfma-vgpr-cd-select.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw-system.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans.ll
M llvm/test/CodeGen/AMDGPU/mubuf-offset-private.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
M llvm/test/CodeGen/AMDGPU/mul_int24.ll
M llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
M llvm/test/CodeGen/AMDGPU/multilevel-break.ll
M llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll
M llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
M llvm/test/CodeGen/AMDGPU/omod.ll
M llvm/test/CodeGen/AMDGPU/optimize-compare.ll
M llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
M llvm/test/CodeGen/AMDGPU/or.ll
M llvm/test/CodeGen/AMDGPU/pack.v2f16.ll
M llvm/test/CodeGen/AMDGPU/pack.v2i16.ll
M llvm/test/CodeGen/AMDGPU/packed-op-sel.ll
M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
M llvm/test/CodeGen/AMDGPU/partial-shift-shrink.ll
M llvm/test/CodeGen/AMDGPU/permlane-op-sel.ll
M llvm/test/CodeGen/AMDGPU/permlane16_opsel.ll
M llvm/test/CodeGen/AMDGPU/permute.ll
M llvm/test/CodeGen/AMDGPU/permute_i8.ll
M llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll
M llvm/test/CodeGen/AMDGPU/preload-kernarg-header.ll
M llvm/test/CodeGen/AMDGPU/preload-kernargs.ll
M llvm/test/CodeGen/AMDGPU/private-memory-atomics.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/ptr-buffer-alias-scheduling.ll
M llvm/test/CodeGen/AMDGPU/rcp-pattern.ll
M llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-extended-image-insts.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-functions.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-gws.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-s-time.ll
M llvm/test/CodeGen/AMDGPU/rotl.ll
M llvm/test/CodeGen/AMDGPU/rotr.ll
M llvm/test/CodeGen/AMDGPU/rsq.f32.ll
M llvm/test/CodeGen/AMDGPU/s_addk_i32.ll
M llvm/test/CodeGen/AMDGPU/sad.ll
M llvm/test/CodeGen/AMDGPU/saddo.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.v8i16.ll
M llvm/test/CodeGen/AMDGPU/scc-clobbered-sgpr-to-vmem-spill.ll
M llvm/test/CodeGen/AMDGPU/sdiv.ll
M llvm/test/CodeGen/AMDGPU/sdiv64.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/AMDGPU/select-constant-cttz.ll
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/setcc.ll
M llvm/test/CodeGen/AMDGPU/sext-divergence-driven-isel.ll
M llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
M llvm/test/CodeGen/AMDGPU/sgpr-copy-local-cse.ll
M llvm/test/CodeGen/AMDGPU/shift-and-i128-ubfe.ll
M llvm/test/CodeGen/AMDGPU/shift-and-i64-ubfe.ll
M llvm/test/CodeGen/AMDGPU/shift-i128.ll
M llvm/test/CodeGen/AMDGPU/shl.ll
M llvm/test/CodeGen/AMDGPU/shl.v2i16.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cfg-loop-assert.ll
M llvm/test/CodeGen/AMDGPU/si-unify-exit-multiple-unreachables.ll
M llvm/test/CodeGen/AMDGPU/sibling-call.ll
M llvm/test/CodeGen/AMDGPU/sign_extend.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/simplify-libcalls.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/sitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/smfmac_no_agprs.ll
M llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
M llvm/test/CodeGen/AMDGPU/sopk-compares.ll
M llvm/test/CodeGen/AMDGPU/spill-agpr.ll
M llvm/test/CodeGen/AMDGPU/spill-offset-calculation.ll
M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
M llvm/test/CodeGen/AMDGPU/spill-sgpr-stack-no-sgpr.ll
M llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
M llvm/test/CodeGen/AMDGPU/spill-writelane-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sra.ll
M llvm/test/CodeGen/AMDGPU/srem.ll
M llvm/test/CodeGen/AMDGPU/srem64.ll
M llvm/test/CodeGen/AMDGPU/srl.ll
M llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
M llvm/test/CodeGen/AMDGPU/stack-realign-kernel.ll
M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
M llvm/test/CodeGen/AMDGPU/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll
M llvm/test/CodeGen/AMDGPU/tid-kd-xnack-any.ll
M llvm/test/CodeGen/AMDGPU/tid-kd-xnack-off.ll
M llvm/test/CodeGen/AMDGPU/tid-kd-xnack-on.ll
M llvm/test/CodeGen/AMDGPU/trap-abis.ll
M llvm/test/CodeGen/AMDGPU/trap.ll
M llvm/test/CodeGen/AMDGPU/trunc-combine.ll
M llvm/test/CodeGen/AMDGPU/trunc-store.ll
M llvm/test/CodeGen/AMDGPU/trunc.ll
M llvm/test/CodeGen/AMDGPU/uaddo.ll
M llvm/test/CodeGen/AMDGPU/udiv.ll
M llvm/test/CodeGen/AMDGPU/udiv64.ll
M llvm/test/CodeGen/AMDGPU/udivrem.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/uitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/uniform-cfg.ll
M llvm/test/CodeGen/AMDGPU/uniform-select.ll
M llvm/test/CodeGen/AMDGPU/urem64.ll
M llvm/test/CodeGen/AMDGPU/usubo.ll
M llvm/test/CodeGen/AMDGPU/v_add_u64_pseudo_sdwa.ll
M llvm/test/CodeGen/AMDGPU/v_cmp_gfx11.ll
M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
M llvm/test/CodeGen/AMDGPU/v_madak_f16.ll
M llvm/test/CodeGen/AMDGPU/v_pack.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/AMDGPU/v_sub_u64_pseudo_sdwa.ll
M llvm/test/CodeGen/AMDGPU/vector-extract-insert.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/waterfall_kills_scc.ll
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
M llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
M llvm/test/CodeGen/AMDGPU/xor.ll
M llvm/test/CodeGen/AMDGPU/zext-divergence-driven-isel.ll
M llvm/test/CodeGen/MIR/AMDGPU/long-branch-reg-all-sgpr-used.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/flat_atomic.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
Log Message:
-----------
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
This reverts commit adaff46d087799072438dd744b038e6fd50a2d78.
Drop the -O3 checks from default-attributes.hip. I don't know why they
are different on some bots but reverting this is far too disruptive.
Commit: b037d0f0e5f6c7ab528fe3ed9d855f0d770c6709
https://github.com/llvm/llvm-project/commit/b037d0f0e5f6c7ab528fe3ed9d855f0d770c6709
Author: Paschalis Mpeis <paschalis.mpeis at arm.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
A bolt/docs/HeatmapHeader.png
M bolt/docs/Heatmaps.md
Log Message:
-----------
[BOLT][docs] Expand Heatmaps.md (#98162)
Improve documentation on heatmaps.
Add example for X axis labels.
Commit: 94279ae4ca2f6bca7eac4c5e7f572ec66b1c4e0f
https://github.com/llvm/llvm-project/commit/94279ae4ca2f6bca7eac4c5e7f572ec66b1c4e0f
Author: Yeting Kuo <46629943+yetingk at users.noreply.github.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll
Log Message:
-----------
[RISCV] Recommit "Expand vp.stride.load to splat of a scalar load." (#98579)
This is a recommit of #98140. The old commit should be rebased on #98205
which changes the feature of hardware zero stride optimization.
It's a similar patch as a214c521f8763b36dd400b89017f74ad5ae4b6c7 for
vp.stride.load. Some targets prefer pattern (vmv.v.x (load)) instead of
vlse with zero stride.
Commit: de3e9d4138abeb92428bba5014af2f3d9ac21323
https://github.com/llvm/llvm-project/commit/de3e9d4138abeb92428bba5014af2f3d9ac21323
Author: Renato Golin <rengolin at systemcall.eu>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/IR/LinalgNamedStructuredOps.yaml
M mlir/python/mlir/dialects/linalg/opdsl/lang/comprehension.py
M mlir/python/mlir/dialects/linalg/opdsl/ops/core_named_ops.py
Log Message:
-----------
[MLIR][Linalg] Fix named structured ops yaml file (#98865)
Added missing reciprocal to Python file and fixed ErfOp name in yaml
file. Now running the bash script yields the same output.
Commit: 9f4a25e2a7cd176bd4f946dc651bc18c7a2e8c92
https://github.com/llvm/llvm-project/commit/9f4a25e2a7cd176bd4f946dc651bc18c7a2e8c92
Author: Dominik Steenken <dost at de.ibm.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M lld/test/ELF/systemz-gotent-relax-und-dso.s
M lld/test/ELF/systemz-gotent-relax.s
M lld/test/ELF/systemz-init-padding.s
M lld/test/ELF/systemz-plt.s
M llvm/lib/Target/SystemZ/SystemZInstrFormats.td
M llvm/lib/Target/SystemZ/SystemZInstrInfo.td
M llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
M llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
M llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
M llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
M llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
M llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
M llvm/test/MC/Disassembler/SystemZ/insns.txt
M llvm/test/MC/SystemZ/insn-good-z15.s
M llvm/test/MC/SystemZ/insn-good-z196.s
M llvm/test/MC/SystemZ/insn-good-zEC12.s
M llvm/test/MC/SystemZ/insn-good.s
Log Message:
-----------
Add extended mnemonics (#97571)
This PR adds a number of thus-far missing extended mnemonics to the
assembler and disassembler for SystemZ.
The following mnemonics have been added and are supported for the
assembler and disassembler:
- `NOP(R)?`
- `LFI`
- `RISBG(N)?Z`
The following mnemonics have been added and are supported for the
assembler only:
- `JC(TH)?`
- `LLG(F|H)I`
- `NOT(G)?R`
Commit: 8fcb822da632ab4330b47641826ace01af0768e0
https://github.com/llvm/llvm-project/commit/8fcb822da632ab4330b47641826ace01af0768e0
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M llvm/test/Transforms/LoopVectorize/X86/pointer-runtime-checks-unprofitable.ll
Log Message:
-----------
[LV] Add uses of result to pointer-runtime-checks-unprofitable.ll test.
Otherwise %p.2 is not used and will be removed by VPlan transforms,
leading to a difference between legacy and VPlan-based cost.
Commit: e8e406041e93e50d6f8259d2793dfbd08dd43b4a
https://github.com/llvm/llvm-project/commit/e8e406041e93e50d6f8259d2793dfbd08dd43b4a
Author: Ulrich Weigand <ulrich.weigand at de.ibm.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
A llvm/test/CodeGen/SystemZ/vec-cmp-08.ll
Log Message:
-----------
Fix sext_in_reg from i1 to i128
The combineSIGN_EXTEND_INREG routine was using
DAG.getConstant(-1, DL, VT), which does not result in
the expected value when VT has more than 64 bits.
Fix this by using DAG.getAllOnesConstant(DL, VT) instead.
Also add test cases for v1i128 comparisons (which triggers
the bug).
Commit: e027017337cc8ae6ed03dc2a3d1c9903ea2f33b2
https://github.com/llvm/llvm-project/commit/e027017337cc8ae6ed03dc2a3d1c9903ea2f33b2
Author: goldsteinn <35538541+goldsteinn at users.noreply.github.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M llvm/include/llvm/IR/PatternMatch.h
M llvm/unittests/IR/PatternMatch.cpp
Log Message:
-----------
[PatternMatch] Fix issue of stale reference in new `m_{I,F,}Cmp` matchers (#98866)
The new matchers don't output pred. Previously we where just creating
a value on the stack and using it as a dummy output for the matchers,
but this results in a stale reference upon return.
To fix, this patch changes the output variable to a pointer, and
passes in `nullptr` for the matchers that don't output `pred.`
Commit: 9cc599b7ebd0d0dec31f2b384b61f679abbf2ce5
https://github.com/llvm/llvm-project/commit/9cc599b7ebd0d0dec31f2b384b61f679abbf2ce5
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M mlir/test/Dialect/Vector/vector-transfer-collapse-inner-most-dims.mlir
Log Message:
-----------
[mlir][vector] Update tests for collapse 5/n (nfc) (#96227)
The main goal of this PR (and subsequent PRs), is to add more tests with
scalable vectors to:
* vector-transfer-collapse-inner-most-dims.mlir
There's quite a few cases to consider, hence this is split into multiple
PRs. In this PR, I am simply adding more tests for
`vector.transfer_write` so that for every test for `xfer_read`, there's
a corresponding test for `xfer_write`.
This is a follow-up for: #94490, #94604, #94906, #96214
Commit: eb656ea6d7d2284fc7a8f5f9ef46fc19a18f7f3f
https://github.com/llvm/llvm-project/commit/eb656ea6d7d2284fc7a8f5f9ef46fc19a18f7f3f
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll
Log Message:
-----------
[VectorCombine] Add vectorcombine specific test coverage for #98334
Don't rely on phaseordering tests alone
Commit: 054d7b1283a5ebdf724f3ebc38b47e419f8f7a7f
https://github.com/llvm/llvm-project/commit/054d7b1283a5ebdf724f3ebc38b47e419f8f7a7f
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
A llvm/test/CodeGen/X86/huge-stack.ll
Log Message:
-----------
[X86] Add huge-stack.ll test coverage from #84114
Ensure we have -verify-machineinstrs to avoid EXPENSIVE_CHECKS fails
Commit: c2580afed7e55f13762d56400dc346f222ea5884
https://github.com/llvm/llvm-project/commit/c2580afed7e55f13762d56400dc346f222ea5884
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] Convert shift+clamp -> avx2 shift folds to use SDPatternMatch::m_SetCC. NFC.
Commit: 967eba07549d64f15e7a91e798aa46214704f62b
https://github.com/llvm/llvm-project/commit/967eba07549d64f15e7a91e798aa46214704f62b
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
A llvm/test/Transforms/LoopVectorize/X86/divs-with-tail-folding.ll
Log Message:
-----------
[LV] Add test cases for tail-folding sdiv/udiv/urem feeding geps.
Based on reduced tests from
https://github.com/llvm/llvm-project/issues/94328.
Commit: 03d8f9588f143972c0d6af16a8dd8b6a2bfbf1f8
https://github.com/llvm/llvm-project/commit/03d8f9588f143972c0d6af16a8dd8b6a2bfbf1f8
Author: Sergio Afonso <safonsof at amd.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
Log Message:
-----------
[MLIR][OpenMP] NFC: Address tablegen warnings (#98485)
After the addition of the `-verify-openmp-ops` tablegen pseudo-backend
to report suspected issues with the definition of an operation, some
warnings were triggered in the current implementation of OpenMPOps.td.
These are related to known limitations for which TODO messages exist
within these operation's definitions. This patch explicitly inhibits the
inheritance of the `assemblyFormat` property of all clauses added to the
`omp.parallel` and `omp.wsloop` operations to avoid these warnings. This
should help identifying actual issues that may arise later as the
dialect continues to be developed.
Commit: 0d5db4e7ba59bd9cbd956beff8d672a239c9ea12
https://github.com/llvm/llvm-project/commit/0d5db4e7ba59bd9cbd956beff8d672a239c9ea12
Author: chuongg3 <chuong.goh at arm.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-concat-vectors.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
M llvm/test/CodeGen/AArch64/concat-vector.ll
M llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll
Log Message:
-----------
[AArch64][GlobalISel] Bitcast and Build Illegal G_CONCAT_VECTOR Instructions (#96492)
Attempts to handle illegal G_CONCAT_VECTOR instructions by bitcasting the source
into scalar values and using G_BUILD_VECTOR instead
Treating the G_CONCAT_VECTORS instruction in the legalization artefact by folding
away concat(bitcast, ...) into buildvector(...) would require check for ImpDef created
by the shuffles in llvm.
Commit: 2b5595b06c0b7fff4a8dd768612b9a52727c38ab
https://github.com/llvm/llvm-project/commit/2b5595b06c0b7fff4a8dd768612b9a52727c38ab
Author: Kazu Hirata <kazu at google.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M llvm/include/llvm/IR/Instruction.h
Log Message:
-----------
[IR] Remove variants of dropUnknownNonDebugMetadata (#98854)
This patch removes:
- dropUnknownNonDebugMetadata()
- dropUnknownNonDebugMetadata(ID1)
- dropUnknownNonDebugMetadata(ID1, ID2)
The first variant has existing uses, but we can accommodate those by
adding a default parameter to the main variant.
The second and third variant do not have any existing use AFAICT.
Commit: 6484655f9dd07c6d5669dd540feef3c80af84827
https://github.com/llvm/llvm-project/commit/6484655f9dd07c6d5669dd540feef3c80af84827
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M clang/lib/AST/Interp/Interp.cpp
M clang/test/AST/Interp/literals.cpp
Log Message:
-----------
[clang][Interp] Allow initialization of extern variables via ctors
Commit: 59e56eeb1d9c0d25a522ae09f501a350981a31de
https://github.com/llvm/llvm-project/commit/59e56eeb1d9c0d25a522ae09f501a350981a31de
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/ExprCXX.h
M clang/include/clang/AST/Stmt.h
M clang/include/clang/AST/UnresolvedSet.h
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Parse/Parser.h
M clang/include/clang/Sema/DeclSpec.h
M clang/include/clang/Sema/Lookup.h
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ExprCXX.cpp
M clang/lib/AST/ItaniumMangle.cpp
M clang/lib/Parse/ParseExpr.cpp
M clang/lib/Parse/ParseExprCXX.cpp
M clang/lib/Sema/SemaCXXScopeSpec.cpp
M clang/lib/Sema/SemaCoroutine.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaExprMember.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaStmtAsm.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReaderStmt.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
M clang/test/CXX/basic/basic.lookup/basic.lookup.classref/p1-cxx11.cpp
M clang/test/CXX/basic/basic.lookup/basic.lookup.classref/p1.cpp
R clang/test/CXX/basic/basic.lookup/basic.lookup.qual/basic.lookup.qual.general/p3-example3.cpp
R clang/test/CXX/basic/basic.lookup/basic.lookup.qual/basic.lookup.qual.general/p3.cpp
M clang/test/CXX/class.derived/class.member.lookup/p8.cpp
M clang/test/CXX/drs/cwg1xx.cpp
R clang/test/CXX/temp/temp.names/p3-23.cpp
M clang/test/CXX/temp/temp.res/p3.cpp
M clang/test/FixIt/fixit.cpp
M clang/test/Misc/warning-flags.c
M clang/test/Parser/cxx2a-concepts-requires-expr.cpp
M clang/test/SemaCXX/cxx0x-noexcept-expression.cpp
M clang/test/SemaCXX/pseudo-destructors.cpp
M clang/test/SemaCXX/static-assert-cxx17.cpp
M clang/test/SemaTemplate/dependent-base-classes.cpp
M clang/test/SemaTemplate/dependent-template-recover.cpp
M clang/test/SemaTemplate/temp_arg_nontype_cxx20.cpp
M clang/test/SemaTemplate/template-id-expr.cpp
M clang/test/SemaTemplate/typename-specifier-3.cpp
M libcxx/include/regex
M llvm/include/llvm/ADT/ArrayRef.h
Log Message:
-----------
Revert "Reapply "[Clang] Implement resolution for CWG1835 (#92957)" (#98547)"
This reverts commit ce4aada6e2135e29839f672a6599db628b53295d and a
follow-up patch 8ef26f1289bf069ccc0d6383f2f4c0116a1206c1.
This new warning can not be fully suppressed by the
`-Wno-missing-dependent-template-keyword` flag, this gives developer no
time to do the cleanup in a large codebase, see https://github.com/llvm/llvm-project/pull/98547#issuecomment-2228250884
Commit: 1663ac523cae7c8e5818e0fb742591a6ee09a56c
https://github.com/llvm/llvm-project/commit/1663ac523cae7c8e5818e0fb742591a6ee09a56c
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M llvm/test/CodeGen/AMDGPU/gfx10-twoaddr-fma.mir
M llvm/test/CodeGen/AMDGPU/twoaddr-fma-f64.mir
M llvm/test/CodeGen/AMDGPU/twoaddr-fma.mir
M llvm/test/CodeGen/AMDGPU/twoaddr-mad.mir
M llvm/test/CodeGen/AMDGPU/twoaddr-wmma.mir
Log Message:
-----------
[AMDGPU] Remove some invalid tests (#98796)
`-early-live-intervals` only affects default pipeline. If
`LiveIntervalsAnalysis` happens before `TwoAddressInstructionPass`,
`llc` will crash, by adding `-run-pass liveintervals`.
Commit: b42c332d734319c8a522fa3a24642550bac5d653
https://github.com/llvm/llvm-project/commit/b42c332d734319c8a522fa3a24642550bac5d653
Author: jameshu15869 <55058507+jameshu15869 at users.noreply.github.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M libc/benchmarks/gpu/CMakeLists.txt
M libc/benchmarks/gpu/LibcGpuBenchmark.cpp
M libc/benchmarks/gpu/LibcGpuBenchmark.h
Log Message:
-----------
[libc] Use Atomics in GPU Benchmarks (#98842)
This PR replaces our old method of reducing the benchmark results by
using an array to using atomics instead. This should help us implement
single threaded benchmarks.
Commit: cf230e7799472f9a920052e1ef7f1e70e8b0b938
https://github.com/llvm/llvm-project/commit/cf230e7799472f9a920052e1ef7f1e70e8b0b938
Author: Vikram Hegde <115221833+vikramRH at users.noreply.github.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/global_atomic_optimizer_fp_rtn.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_optimizer_fp_no_rtn.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
Log Message:
-----------
[AMDGPU] Enable atomic optimizer for divergent i64 and double values (#96934)
Commit: 0bfdc4d49285edca17a364a8d58cd60d5757c128
https://github.com/llvm/llvm-project/commit/0bfdc4d49285edca17a364a8d58cd60d5757c128
Author: Zahira Ammarguellat <zahira.ammarguellat at intel.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/test/CodeGen/X86/math-builtins.c
M clang/test/CodeGen/constrained-math-builtins.c
Log Message:
-----------
Add __builtin_fmaf16. (#97424)
Commit: 93d7d9bfd4aede19dda0ebaf8aead12c2adbd13b
https://github.com/llvm/llvm-project/commit/93d7d9bfd4aede19dda0ebaf8aead12c2adbd13b
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M llvm/test/Transforms/InstSimplify/and-or-implied-cond.ll
Log Message:
-----------
[InstSimplify] Add test for #98753 (NFC)
Commit: 1af3a89a4b384cbc5a6b111a0f7756085de818cd
https://github.com/llvm/llvm-project/commit/1af3a89a4b384cbc5a6b111a0f7756085de818cd
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M clang/test/C/C2y/n3244.c
Log Message:
-----------
Correct test for 32-bit systems
Addresses an issue found in post-commit.
Commit: a972a394afcb276abb3029d0f2753d4403e379c2
https://github.com/llvm/llvm-project/commit/a972a394afcb276abb3029d0f2753d4403e379c2
Author: Thomas Wucher <30866545+thomaswucher at users.noreply.github.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M clang/bindings/python/clang/cindex.py
M clang/bindings/python/tests/cindex/test_cursor.py
M clang/bindings/python/tests/cindex/test_enums.py
M clang/docs/ReleaseNotes.rst
M clang/include/clang-c/Index.h
A clang/test/Index/binop.cpp
M clang/test/Index/blocks.c
M clang/test/Index/c-index-api-loadTU-test.m
M clang/test/Index/index-concepts.cpp
M clang/test/Index/load-staticassert.cpp
M clang/test/Index/nested-binaryoperators.cpp
M clang/test/Index/preamble.c
M clang/test/Index/print-type.c
M clang/test/Index/print-type.cpp
M clang/test/Index/recursive-cxx-member-calls.cpp
M clang/test/Index/remap-load.c
M clang/test/Index/usrs.m
M clang/tools/c-index-test/c-index-test.c
M clang/tools/libclang/CIndex.cpp
M clang/tools/libclang/libclang.map
Log Message:
-----------
Retrieve BinaryOperator::getOpcode and BinaryOperator::getOpcodeStr via libclang and its python interface (#98489)
This is a rework of patch [D10833](https://reviews.llvm.org/D10833)
previously posted on LLVM Phabricator by arthurp in 2015. It allows to
retrieve the type of binary operator via libclangs python bindings.
I did clean up the changes, removed unrelated changes and rebased the
changeset to the latest main branch. As this is my first contribution to
the LLVM project, let me know if any required tests or documentation are
missing.
Commit: 861a8ed68be7c6d5e2605b1ab3810fde72b5f66a
https://github.com/llvm/llvm-project/commit/861a8ed68be7c6d5e2605b1ab3810fde72b5f66a
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M clang/lib/Sema/SemaOpenMP.cpp
Log Message:
-----------
[clang][OpenMP] Remove compound directives from `checkNestingOfRegions` (#98387)
Express the constraints via constituent directives.
Commit: bd04ac0694cc9fb3c43a4acb2f7cd1db08eba673
https://github.com/llvm/llvm-project/commit/bd04ac0694cc9fb3c43a4acb2f7cd1db08eba673
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M clang/tools/libclang/CIndex.cpp
Log Message:
-----------
Fix "default label in switch which covers all enumeration values" warning; NFC
Amends a972a394afcb276abb3029d0f2753d4403e379c2
Commit: 4ed0f84d3897ba2f3c05f94342d9423cab61f86b
https://github.com/llvm/llvm-project/commit/4ed0f84d3897ba2f3c05f94342d9423cab61f86b
Author: Jan Patrick Lehr <JanPatrick.Lehr at amd.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M offload/test/api/omp_dynamic_shared_memory_amdgpu.c
M offload/test/api/omp_dynamic_shared_memory_mixed_amdgpu.c
M offload/test/offloading/bug51781.c
M offload/test/offloading/bug51982.c
Log Message:
-----------
[Offload] XFAIL four tests while working on fix (#98899)
omp_dynamic_shared_memory_mixed_amdgpu.c
omp_dynamic_shared_memory_amdgpu.c
amdgcn-amd-amdhsa::bug51982.c
amdgcn-amd-amdhsa::bug51781.c
Commit: a1dfe15632170342ae073d7238294dfe224682ed
https://github.com/llvm/llvm-project/commit/a1dfe15632170342ae073d7238294dfe224682ed
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M clang/lib/Sema/SemaOpenMP.cpp
Log Message:
-----------
[clang][OpenMP] Simplify check for taskloop in `ActOnOpenMPLoopInitia… (#98633)
…lization`
Replace the explicit list of compound directives ending with taskloop
with checking for the last leaf construct.
Commit: 075f7542f1b55695b871fb5d6359c2350af474f8
https://github.com/llvm/llvm-project/commit/075f7542f1b55695b871fb5d6359c2350af474f8
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp
A llvm/test/tools/llvm-split/AMDGPU/declarations.ll
Log Message:
-----------
[AMDGPU][llvm-split] Fix division by zero (#98888)
An empty module, or one containing only declarations, would result in a
division by a zero cost.
Commit: e73cf2f0c5b437f944e9a796d96d550d6ae3d8cf
https://github.com/llvm/llvm-project/commit/e73cf2f0c5b437f944e9a796d96d550d6ae3d8cf
Author: Matthias Springer <me at m-sp.org>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M flang/include/flang/Tools/CLOptions.inc
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/CodeGen/TypeConverter.cpp
M flang/test/Fir/basic-program.fir
Log Message:
-----------
[flang] Remove materialization workaround in type converter (#98743)
This change is in preparation of #97903, which adds extra checks for
materializations: it is now enforced that they produce an SSA value of
the correct type, so the current workaround no longer works.
The original workaround avoided target materializations by directly
returning the to-be-converted SSA value from the materialization
callback. This can be avoided by initializing the lowering patterns that
insert the materializations without a type converter. For
`cg::XEmboxOp`, the existing workaround that skips
`unrealized_conversion_cast` ops is still in place.
Also remove the lowering pattern for `unrealized_conversion_cast`. This
pattern has no effect because `unrealized_conversion_cast` ops that are
inserted by the dialect conversion framework are never matched by the
pattern driver.
Commit: 97ebc9794941d9e73792ab9deab7abafaf750a17
https://github.com/llvm/llvm-project/commit/97ebc9794941d9e73792ab9deab7abafaf750a17
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M clang/lib/Sema/SemaOpenMP.cpp
Log Message:
-----------
[clang[OpenMP] Revert accidentally included changes from previous commit
Commit: ef51e617c43ef4248973f07e0a711f69d85c948c
https://github.com/llvm/llvm-project/commit/ef51e617c43ef4248973f07e0a711f69d85c948c
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M libcxx/docs/ReleaseNotes/19.rst
M libcxx/include/barrier
M libcxx/include/future
M libcxx/include/ios
M libcxx/include/latch
M libcxx/include/locale
M libcxx/include/locale.h
M libcxx/include/semaphore
M libcxx/include/shared_mutex
M libcxx/include/stop_token
M libcxx/include/thread
Log Message:
-----------
[libc++] Handle _LIBCPP_HAS_NO_{THREADS,LOCALIZATION} consistently with other carve-outs (#98319)
Previously, we would issue an #error when using a header that requires
threading support or localization support in a configuration where that
is disabled. This is unlike what we do for all the other carve outs like
no-filesystem, no-wide-characters or no-random-device. Instead of
issuing an #error, we normally just remove the problematic parts of the
header.
This patch makes the handling of no-localization and no-threads
consistent with the other carve-outs. I dislike the fact that users
won't get an explicit error message when trying to use e.g. ios in a
build that doesn't support localization, but I think it is better to
handle things consistently. Note that besides the consistency argument,
the #error approach doesn't really work anyways since it would break
down if we moved towards assuming the C locale only in the
no-localization mode.
Commit: 1612e4a3510982692f22e3f8190fc7c977185cbe
https://github.com/llvm/llvm-project/commit/1612e4a3510982692f22e3f8190fc7c977185cbe
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
Log Message:
-----------
Revert "[AMDGPU] Do not use original PHIs in coercion chains (#98063)"
This reverts commit dc8ea046a516c3bdd0ece306f406c9ea833d4dac.
It generated broken IR as described here:
https://github.com/llvm/llvm-project/pull/98063#issuecomment-2225259451
Commit: 4420c57fc395385eb039cb7c30d71ee29628c7de
https://github.com/llvm/llvm-project/commit/4420c57fc395385eb039cb7c30d71ee29628c7de
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M llvm/test/CodeGen/AMDGPU/amdgpu-late-codegenprepare.ll
Log Message:
-----------
[AMDGPU] Add a test case for #98063
Add a test case to demonstrate broken IR caused by #98063 "[AMDGPU] Do
not use original PHIs in coercion chains" before it was reverted.
Commit: 9ba9e480fa4ef1f37a2b6b51603ac8e446cca5ff
https://github.com/llvm/llvm-project/commit/9ba9e480fa4ef1f37a2b6b51603ac8e446cca5ff
Author: Petr Hosek <phosek at google.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M libc/src/__support/OSUtil/baremetal/io.cpp
Log Message:
-----------
[libc] Mark external baremetal I/O symbols as extern "C" (#98871)
These need to use C ABI.
Commit: beccecaacde405a3b50891c67594eccbcd1c8b08
https://github.com/llvm/llvm-project/commit/beccecaacde405a3b50891c67594eccbcd1c8b08
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/select-reduction-op.ll
Log Message:
-----------
[SLP]Fix PR98838: do no replace condition of select-based logical op by poison.
If the reduction operation is a select-based logical op, the condition
should be replaced by the poison, better to replace by the non-poisoning
constant to prevent poison propagation in the vector code.
Fixes https://github.com/llvm/llvm-project/issues/98838
Commit: dd7d81ea49bf39e1d69bbb84bd3f31bd95519369
https://github.com/llvm/llvm-project/commit/dd7d81ea49bf39e1d69bbb84bd3f31bd95519369
Author: Johannes Reifferscheid <jreiffers at google.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M mlir/lib/IR/AffineExpr.cpp
M mlir/unittests/IR/AffineExprTest.cpp
Log Message:
-----------
Fix simplification of x + x//c*-c to x mod c. (#98909)
There was no check that rhs is actually a multiplication.
Commit: acc159aea1e641e3694ab8fe5faa231788077011
https://github.com/llvm/llvm-project/commit/acc159aea1e641e3694ab8fe5faa231788077011
Author: Matthias Springer <me at m-sp.org>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M mlir/docs/DialectConversion.md
M mlir/include/mlir/Dialect/SCF/TransformOps/SCFTransformOps.td
M mlir/include/mlir/Transforms/DialectConversion.h
M mlir/lib/Conversion/LLVMCommon/TypeConverter.cpp
M mlir/lib/Dialect/SCF/TransformOps/CMakeLists.txt
M mlir/lib/Dialect/SCF/TransformOps/SCFTransformOps.cpp
M mlir/lib/Transforms/Utils/DialectConversion.cpp
M mlir/test/Conversion/FuncToLLVM/func-memref-return.mlir
A mlir/test/Transforms/test-block-legalization.mlir
Log Message:
-----------
[mlir][Transforms] Dialect conversion: Fix missing source materialization (#97903)
This commit fixes a bug in the dialect conversion. During a 1:N
signature conversion, the dialect conversion did not insert a cast back
to the original block argument type, producing invalid IR.
See `test-block-legalization.mlir`: Without this commit, the operand
type of the op changes because an `unrealized_conversion_cast` is
missing:
```
"test.consumer_of_complex"(%v) : (!llvm.struct<(f64, f64)>) -> ()
```
To implement this fix, it was necessary to change the meaning of
argument materializations. An argument materialization now maps from the
new block argument types to the original block argument type. (It now
behaves almost like a source materialization.) This also addresses a
`FIXME` in the code base:
```
// FIXME: The current argument materialization hook expects the original
// output type, even though it doesn't use that as the actual output type
// of the generated IR. The output type is just used as an indicator of
// the type of materialization to do. This behavior is really awkward in
// that it diverges from the behavior of the other hooks, and can be
// easily misunderstood. We should clean up the argument hooks to better
// represent the desired invariants we actually care about.
```
It is no longer necessary to distinguish between the "output type" and
the "original output type".
Most type converter are already written according to the new API. (Most
implementations use the same conversion functions as for source
materializations.) One exception is the MemRef-to-LLVM type converter,
which materialized an `!llvm.struct` based on the elements of a memref
descriptor. It still does that, but casts the `!llvm.struct` back to the
original memref type. The dialect conversion inserts a target
materialization (to `!llvm.struct`) which cancels out with the other
cast.
This commit also fixes a bug in `computeNecessaryMaterializations`. The
implementation did not account for the possibility that a value was
replaced multiple times. E.g., replace `a` by `b`, then `b` by `c`.
This commit also adds a transform dialect op to populate SCF-to-CF
patterns. This transform op was needed to write a test case. The bug
described here appears only during a complex interplay of 1:N signature
conversions and op replacements. (I was not able to trigger it with ops
and patterns from the `test` dialect without duplicating the `scf.if`
pattern.)
Note for LLVM integration: Make sure that all
`addArgument/Source/TargetMaterialization` functions produce an SSA of
the specified type.
Depends on #98743.
Commit: 94efdff84a8f6d52915b90b705fe991f4888c544
https://github.com/llvm/llvm-project/commit/94efdff84a8f6d52915b90b705fe991f4888c544
Author: Jonathan Thackray <jonathan.thackray at arm.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M clang/docs/CommandGuide/clang.rst
Log Message:
-----------
[AArch64][RISCV] Document option --print-supported-extensions (#98698)
Add documentation for the `--print-supported-extensions`
option which appears to be missing at present.
Commit: 88f0dc48d6f46e1677dc679ae649e9b291140b13
https://github.com/llvm/llvm-project/commit/88f0dc48d6f46e1677dc679ae649e9b291140b13
Author: OverMighty <its.overmighty at gmail.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M libc/test/src/__support/CPP/type_traits_test.cpp
M libc/test/src/__support/FPUtil/fpbits_test.cpp
M libc/test/src/__support/big_int_test.cpp
M libc/test/src/math/RoundToIntegerTest.h
M libc/test/src/math/smoke/FMaxTest.h
M libc/test/src/math/smoke/FMaximumMagNumTest.h
M libc/test/src/math/smoke/FMaximumMagTest.h
M libc/test/src/math/smoke/FMaximumNumTest.h
M libc/test/src/math/smoke/FMaximumTest.h
M libc/test/src/math/smoke/FMinTest.h
M libc/test/src/math/smoke/FMinimumMagNumTest.h
M libc/test/src/math/smoke/FMinimumMagTest.h
M libc/test/src/math/smoke/FMinimumNumTest.h
M libc/test/src/math/smoke/FMinimumTest.h
M libc/test/src/math/smoke/FModTest.h
M libc/test/src/math/smoke/FrexpTest.h
M libc/test/src/math/smoke/ILogbTest.h
M libc/test/src/math/smoke/LogbTest.h
M libc/test/src/stdio/sprintf_test.cpp
M libc/test/src/string/memory_utils/op_tests.cpp
Log Message:
-----------
[libc] Fix warnings emitted by GCC (#98751)
Fixes #98709.
Commit: 4e338dce4de4ca1476e2b8f9c907769691a9093b
https://github.com/llvm/llvm-project/commit/4e338dce4de4ca1476e2b8f9c907769691a9093b
Author: Xiaoyang Liu <siujoeng.lau at gmail.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M libcxx/docs/FeatureTestMacroTable.rst
M libcxx/docs/ReleaseNotes/19.rst
M libcxx/docs/Status/Cxx2cPapers.csv
M libcxx/include/__mdspan/extents.h
M libcxx/include/mdspan
M libcxx/include/version
A libcxx/test/std/containers/views/mdspan/extents/dims.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/mdspan.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp
M libcxx/utils/generate_feature_test_macro_components.py
Log Message:
-----------
[libc++] P2389R2: `dextents` Index Type Parameter (#97393)
This patch implements P2389R2, which was adopted at the St. Louis meeting.
It builds upon previous enhancements from P2299R3, which introduced deduction
guides and the `dextents` alias template.
Commit: 365f5b4a1dfe84f2978a41d5a85672e749056620
https://github.com/llvm/llvm-project/commit/365f5b4a1dfe84f2978a41d5a85672e749056620
Author: Him188 <tguan at nvidia.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir
M llvm/test/CodeGen/AArch64/itofp.ll
Log Message:
-----------
[AArch64][GISel] Add fp128 and i128 sitofp/uitofp handling (#97691)
Legalize sitofp/uitofp involving fp128/i128 types into a libcall.
Vector with i128/fp128 types are scalarized.
Commit: 82af55983d75d4a821b76ee926b19725ec7fa889
https://github.com/llvm/llvm-project/commit/82af55983d75d4a821b76ee926b19725ec7fa889
Author: Vincent Belliard <81770341+v-bulle at users.noreply.github.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M lldb/include/lldb/API/SBValue.h
M lldb/source/API/SBValue.cpp
M lldb/test/API/python_api/formatters/TestFormattersSBAPI.py
M lldb/test/API/python_api/formatters/main.cpp
M lldb/test/API/python_api/formatters/synth.py
Log Message:
-----------
[API] add GetSyntheticValue (#95959)
Adds GetSyntheticValue to the API on top of GetNonSyntheticValue.
---------
Co-authored-by: Vincent Belliard <v-bulle at github.com>
Commit: 6469faf9fd835a0fab6290168949d00e35556e75
https://github.com/llvm/llvm-project/commit/6469faf9fd835a0fab6290168949d00e35556e75
Author: Matthias Springer <me at m-sp.org>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M mlir/test/Integration/GPU/ROCM/gpu-to-hsaco.mlir
M mlir/test/Integration/GPU/ROCM/printf.mlir
M mlir/test/Integration/GPU/ROCM/two-modules.mlir
M mlir/test/Integration/GPU/ROCM/vecadd.mlir
M mlir/test/Integration/GPU/ROCM/vector-transferops.mlir
Log Message:
-----------
[mlir] Fix GPU integration test (#98917)
Fix tests that were broken by #97903.
Commit: deff3afd35d4f301fe74d20cf9b180c79d2b7016
https://github.com/llvm/llvm-project/commit/deff3afd35d4f301fe74d20cf9b180c79d2b7016
Author: Paschalis Mpeis <paschalis.mpeis at arm.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M bolt/include/bolt/Core/MCPlusBuilder.h
M bolt/lib/Passes/Instrumentation.cpp
Log Message:
-----------
[NFC][BOLT] Rename createDummyReturnFunction to createReturnInstructi.. (#98448)
`createDummyReturnFunction` is not creating a function but instead only
a function body that is simply a return statement.
This patch renames it to: `createReturnInstructionList`
Commit: b320d3733dfb76c1b7d78fc499490d34b99e2284
https://github.com/llvm/llvm-project/commit/b320d3733dfb76c1b7d78fc499490d34b99e2284
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/combine-shl.ll
M llvm/test/CodeGen/X86/combine-srl.ll
Log Message:
-----------
[X86] Add handling for select(icmp_uge(amt,BW),0,shift_logical(x,amt)) -> avx2 shift(x,amt)
We need to catch this otherwise pre-AVX512 targets will fold this to and(icmp_ult(amt,BW),shift_logical(x,amt))
Commit: 77e31000db8bd7103b0041b22e654537ceea95f6
https://github.com/llvm/llvm-project/commit/77e31000db8bd7103b0041b22e654537ceea95f6
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M llvm/include/llvm/CodeGen/SDPatternMatch.h
Log Message:
-----------
[DAG] SDPatternMatch::m_SetCC - rename operands. NFC.
Rename operands to make it easier to remember what they each represent.
Commit: ba8792b667a2bb167d6a8ce3b76e14d51258065c
https://github.com/llvm/llvm-project/commit/ba8792b667a2bb167d6a8ce3b76e14d51258065c
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Log Message:
-----------
[X86] visitFCOPYSIGN - pull out repeated SDLoc. NFC.
Commit: 4fac1456d3132e2745ddbfacb326cf0afd613f3c
https://github.com/llvm/llvm-project/commit/4fac1456d3132e2745ddbfacb326cf0afd613f3c
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] combineSelect - reuse existing SDLoc. NFC.
Commit: 903f6fceb86e68b0dbc11b13f808fc00a471e595
https://github.com/llvm/llvm-project/commit/903f6fceb86e68b0dbc11b13f808fc00a471e595
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
Log Message:
-----------
[RISCV] Prune dead LI in vsetvli coalescing with trivially dead vsetvli (#98647)
This is a follow up to ff8a03a7. On the review for that, I'd suggested a
stylistic rework, but after discussion we decided to move forward with
the fix as it was. This change is a small part of that suggested rework.
Once I sat down and wrote the code, I think I've convinced myself of an
entirely different approach (tbd), but for the moment, let's use a
lambda to share code so that we can pickup a missed optimization, and
reduce some duplication.
---------
Co-authored-by: Luke Lau <luke_lau at icloud.com>
Commit: 03fe7a83ce79d43b63052e7762573b57a8c52db8
https://github.com/llvm/llvm-project/commit/03fe7a83ce79d43b63052e7762573b57a8c52db8
Author: Edd Dawson <edd.dawson at sony.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M clang/lib/Driver/ToolChains/PS4CPU.cpp
M clang/lib/Driver/ToolChains/PS4CPU.h
A clang/test/Driver/ps4-linker.c
R clang/test/Driver/ps4-ps5-linker.c
A clang/test/Driver/ps5-linker.c
Log Message:
-----------
[PS4/PS5][NFC] Split PScpu::Linker into PS4/PS5 classes (#98884)
It has long been the case on PlayStation that the linker itself has
taken on much of the responsibility that is traditionally the domain of
the C language driver elsewhere: which linker script to use, selection
of CRT objects, and so forth.
This is changing on PS5. The driver will assume responsibility for such
things. However, the situation on PS4 will remain as-is. To accommodate
this divergence, we must first separate how linker Jobs are created.
`clang/test/Driver/ps4-linker.c` has been similarly split for related
reasons.
In subsequent changes, PS5-specific linking behaviour can be moved from
SIE private patches in the PS5 linker to the (upstream) driver without
affecting the behaviour or implementation of PS4.
Commit: 7775be4d48e95385c1968d7f1826a11e08f5f954
https://github.com/llvm/llvm-project/commit/7775be4d48e95385c1968d7f1826a11e08f5f954
Author: Matthias Springer <me at m-sp.org>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M mlir/test/Integration/GPU/CUDA/async.mlir
Log Message:
-----------
[mlir] Fix GPU integration test (part 2) (#98918)
Fix tests that were broken by #97903.
Commit: 0309709a6786653da7164334c83b09c9f37b943a
https://github.com/llvm/llvm-project/commit/0309709a6786653da7164334c83b09c9f37b943a
Author: Chenguang Wang <w3cing at gmail.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] Add missing dependency for mlir:SCFTransformOps (#98919)
Bazel build failure was introduced in commit acc159ae.
Commit: d5f4f084d29ce95fa27e5b7e80a630ae194df4bb
https://github.com/llvm/llvm-project/commit/d5f4f084d29ce95fa27e5b7e80a630ae194df4bb
Author: Luke Lau <luke at igalia.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll
Log Message:
-----------
[RISCV] Always expand zero strided vp.strided.load (#98901)
This patch makes zero strided VP loads always be expanded to a scalar
load and splat even if +optimized-zero-stride-load is present.
Expanding it allows more .vx splat patterns to be matched, which is
needed to prevent regressions in #98111.
If the feature is present, RISCVISelDAGToDAG will combine it back to a
zero strided load.
The RV32 test diff also shows how need to emit a zero strided load
either way after expanding an SEW=64 strided load. We could maybe fix
this in a later patch by not doing the expand if SEW>XLEN.
Commit: a46d60ad32dbb14d82eda7d18ef7c418a51b22ff
https://github.com/llvm/llvm-project/commit/a46d60ad32dbb14d82eda7d18ef7c418a51b22ff
Author: Max Beck-Jones <max.beck-jones at arm.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
M llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
M llvm/utils/TableGen/DecoderEmitter.cpp
Log Message:
-----------
[NFC] [AArch64] Refactor predicate register class decode functions (#97412)
In a previous PR #81716, a new decoder function was added to
llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp. During
code review it was suggested that, as most of the decoder functions were
very similar in structure, that they be refactored into a single,
templated function. I have added the refactored function, removed the
definitions of the replaced functions, and replaced the references to
the replaced functions in AArch64Disassembler.cpp and
llvm/lib/Target/AArch64/AArch64RegisterInfo.td. To reduce the number of
duplicate references in AArch64RegisterInfo.td, I have also made a small
change to llvm/utils/TableGen/DecoderEmitter.cpp.
Commit: c2fab5a4c69c857061b06b9a826bf4730821e483
https://github.com/llvm/llvm-project/commit/c2fab5a4c69c857061b06b9a826bf4730821e483
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M clang/tools/c-index-test/c-index-test.c
Log Message:
-----------
Fix memory leak in unit test
Commit: 106621b601d7dc7c4929fba293f7e5ffe6b92c58
https://github.com/llvm/llvm-project/commit/106621b601d7dc7c4929fba293f7e5ffe6b92c58
Author: Mikhail R. Gadelha <mikhail at igalia.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M libc/test/UnitTest/LibcTest.cpp
Log Message:
-----------
[libc][NFC] Fix printed test time in 32-bit systems (#98922)
clock() returns a clock_t, which is a long and might overflow in 32-bit
systems when the test takes a long time to run. Changing it to uint64_t
fixes this issue. Before:
[ RUN ] LlvmLibcHashTest.Avalanche
[ OK ] LlvmLibcHashTest.Avalanche (18446744073709551138 ms)
After this patch:
[ RUN ] LlvmLibcHashTest.Avalanche
[ OK ] LlvmLibcHashTest.Avalanche (4154 ms)
Commit: a78b19d8ea513a2e88fa431b549b65406384a12d
https://github.com/llvm/llvm-project/commit/a78b19d8ea513a2e88fa431b549b65406384a12d
Author: Kazu Hirata <kazu at google.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M llvm/lib/IR/Metadata.cpp
Log Message:
-----------
[IR] Use SmallSet with more inline elements in dropUnknownNonDebugMetadata (NFC) (#98853)
SmallSet here often ends up allocating memory via std::set inside
SmallSet because KnownIDs.size() goes up to 17 on an x86 host. This
patch switches to SmallSet<unsigned, 32> to avoid memory
allocations.
The increased inline elements here save 0.57% of heap allocations during
the compilation of X86ISelLowering.cpp.ii, a preprocessed version of
X86ISelLowering.cpp.
Commit: 3560e1d0cefa45285f3063c3f74270bcbd744da3
https://github.com/llvm/llvm-project/commit/3560e1d0cefa45285f3063c3f74270bcbd744da3
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Log Message:
-----------
[DAG] visitADDLike - convert (A-B)+(C-D) --> (A+C)-(B+D) fold to sd_match. NFC.
Commit: 290537238b45106e30bb082b9affde345d8a5482
https://github.com/llvm/llvm-project/commit/290537238b45106e30bb082b9affde345d8a5482
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Log Message:
-----------
[X86] visitADDLike - pull out repeated SDLoc. NFC.
Commit: fd9bdead23e1c994df036efe410191e25e60ed36
https://github.com/llvm/llvm-project/commit/fd9bdead23e1c994df036efe410191e25e60ed36
Author: Fangrui Song <i at maskray.me>
Date: 2024-07-15 (Mon, 15 Jul 2024)
Changed paths:
M bolt/docs/CommandLineArgumentReference.md
A bolt/docs/HeatmapHeader.png
M bolt/docs/Heatmaps.md
M bolt/include/bolt/Core/MCPlusBuilder.h
M bolt/include/bolt/Utils/CommandLineOpts.h
M bolt/lib/Passes/Instrumentation.cpp
M bolt/lib/Profile/Heatmap.cpp
M bolt/lib/Target/X86/X86MCPlusBuilder.cpp
M bolt/lib/Utils/CommandLineOpts.cpp
A bolt/test/AArch64/dummy-return.s
M clang-tools-extra/test/clang-doc/basic-project.test
M clang/bindings/python/clang/cindex.py
M clang/bindings/python/tests/cindex/test_cursor.py
M clang/bindings/python/tests/cindex/test_enums.py
M clang/cmake/caches/Fuchsia-stage2.cmake
M clang/docs/CommandGuide/clang.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang-c/Index.h
M clang/include/clang/AST/ExprCXX.h
M clang/include/clang/AST/Stmt.h
M clang/include/clang/AST/UnresolvedSet.h
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Driver/Options.td
M clang/include/clang/Parse/Parser.h
M clang/include/clang/Sema/DeclSpec.h
M clang/include/clang/Sema/Lookup.h
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/CMakeLists.txt
M clang/lib/AST/ExprCXX.cpp
M clang/lib/AST/Interp/Compiler.cpp
M clang/lib/AST/Interp/Compiler.h
R clang/lib/AST/Interp/DynamicAllocator.cpp
R clang/lib/AST/Interp/DynamicAllocator.h
M clang/lib/AST/Interp/EvalEmitter.cpp
M clang/lib/AST/Interp/EvaluationResult.cpp
M clang/lib/AST/Interp/EvaluationResult.h
M clang/lib/AST/Interp/Interp.cpp
M clang/lib/AST/Interp/Interp.h
M clang/lib/AST/Interp/InterpBlock.h
M clang/lib/AST/Interp/InterpState.cpp
M clang/lib/AST/Interp/InterpState.h
M clang/lib/AST/Interp/Opcodes.td
M clang/lib/AST/Interp/Pointer.h
M clang/lib/AST/ItaniumMangle.cpp
M clang/lib/Basic/Targets/RISCV.cpp
M clang/lib/Basic/Targets/RISCV.h
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CGDecl.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGExprConstant.cpp
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/lib/CodeGen/CGRecordLayoutBuilder.cpp
M clang/lib/CodeGen/CGStmt.cpp
M clang/lib/CodeGen/CodeGenFunction.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/CodeGenTypes.cpp
M clang/lib/CodeGen/CodeGenTypes.h
M clang/lib/Driver/ToolChains/Arch/RISCV.cpp
M clang/lib/Driver/ToolChains/PS4CPU.cpp
M clang/lib/Driver/ToolChains/PS4CPU.h
M clang/lib/Parse/ParseExpr.cpp
M clang/lib/Parse/ParseExprCXX.cpp
M clang/lib/Sema/CMakeLists.txt
M clang/lib/Sema/SemaCXXScopeSpec.cpp
M clang/lib/Sema/SemaCoroutine.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaExprMember.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaStmtAsm.cpp
M clang/lib/Sema/SemaTemplate.cpp
A clang/lib/Sema/SemaTemplateDeductionGuide.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReaderStmt.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
M clang/test/AST/Interp/literals.cpp
R clang/test/AST/Interp/new-delete.cpp
M clang/test/C/C2y/n3244.c
M clang/test/CXX/basic/basic.lookup/basic.lookup.classref/p1-cxx11.cpp
M clang/test/CXX/basic/basic.lookup/basic.lookup.classref/p1.cpp
R clang/test/CXX/basic/basic.lookup/basic.lookup.qual/basic.lookup.qual.general/p3-example3.cpp
R clang/test/CXX/basic/basic.lookup/basic.lookup.qual/basic.lookup.qual.general/p3.cpp
M clang/test/CXX/class.derived/class.member.lookup/p8.cpp
M clang/test/CXX/class/class.compare/class.compare.default/p1.cpp
M clang/test/CXX/drs/cwg1xx.cpp
R clang/test/CXX/temp/temp.names/p3-23.cpp
M clang/test/CXX/temp/temp.res/p3.cpp
M clang/test/CodeGen/X86/math-builtins.c
M clang/test/CodeGen/aarch64-byval-temp.c
M clang/test/CodeGen/attr-noundef.cpp
M clang/test/CodeGen/builtins-bitint.c
M clang/test/CodeGen/builtins-elementwise-math.c
M clang/test/CodeGen/builtins-overflow.c
M clang/test/CodeGen/constrained-math-builtins.c
M clang/test/CodeGen/ext-int-cc.c
M clang/test/CodeGen/ext-int-sanitizer.cpp
M clang/test/CodeGen/ext-int.c
M clang/test/CodeGen/extend-arg-64.c
M clang/test/CodeGen/ubsan-shift-bitint.c
M clang/test/CodeGenCXX/ext-int.cpp
M clang/test/CodeGenHIP/default-attributes.hip
M clang/test/CodeGenHIP/printf_nonhostcall.cpp
M clang/test/CodeGenHLSL/builtins/dot-builtin.hlsl
A clang/test/Driver/ps4-linker.c
R clang/test/Driver/ps4-ps5-linker.c
A clang/test/Driver/ps5-linker.c
M clang/test/Driver/riscv-features.c
M clang/test/FixIt/fixit.cpp
M clang/test/Frontend/fixed_point_comparisons.c
A clang/test/Index/binop.cpp
M clang/test/Index/blocks.c
M clang/test/Index/c-index-api-loadTU-test.m
M clang/test/Index/index-concepts.cpp
M clang/test/Index/load-staticassert.cpp
M clang/test/Index/nested-binaryoperators.cpp
M clang/test/Index/preamble.c
M clang/test/Index/print-type.c
M clang/test/Index/print-type.cpp
M clang/test/Index/recursive-cxx-member-calls.cpp
M clang/test/Index/remap-load.c
M clang/test/Index/usrs.m
M clang/test/Misc/warning-flags.c
M clang/test/OpenMP/distribute_parallel_for_simd_if_codegen.cpp
M clang/test/OpenMP/parallel_master_taskloop_simd_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_if_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_if_codegen.cpp
M clang/test/OpenMP/target_teams_generic_loop_if_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_if_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_if_codegen.cpp
M clang/test/OpenMP/teams_distribute_simd_codegen.cpp
M clang/test/Parser/cxx2a-concepts-requires-expr.cpp
M clang/test/Rewriter/rewrite-modern-catch.m
M clang/test/SemaCXX/cxx0x-noexcept-expression.cpp
M clang/test/SemaCXX/delete.cpp
M clang/test/SemaCXX/new-delete.cpp
M clang/test/SemaCXX/pseudo-destructors.cpp
M clang/test/SemaCXX/static-assert-cxx17.cpp
M clang/test/SemaTemplate/dependent-base-classes.cpp
M clang/test/SemaTemplate/dependent-template-recover.cpp
M clang/test/SemaTemplate/temp_arg_nontype_cxx20.cpp
M clang/test/SemaTemplate/template-id-expr.cpp
M clang/test/SemaTemplate/typename-specifier-3.cpp
M clang/tools/c-index-test/c-index-test.c
M clang/tools/libclang/CIndex.cpp
M clang/tools/libclang/libclang.map
M compiler-rt/lib/nsan/nsan.cpp
M flang/docs/Intrinsics.md
M flang/include/flang/Optimizer/Builder/IntrinsicCall.h
M flang/include/flang/Optimizer/Builder/Runtime/Intrinsics.h
M flang/include/flang/Runtime/misc-intrinsic.h
M flang/include/flang/Tools/CLOptions.inc
M flang/lib/Evaluate/intrinsics.cpp
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/lib/Optimizer/Builder/Runtime/Intrinsics.cpp
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/CodeGen/TypeConverter.cpp
M flang/runtime/misc-intrinsic.cpp
M flang/test/Fir/basic-program.fir
A flang/test/Lower/Intrinsics/rename.f90
M flang/test/Lower/namelist.f90
M libc/benchmarks/gpu/CMakeLists.txt
M libc/benchmarks/gpu/LibcGpuBenchmark.cpp
M libc/benchmarks/gpu/LibcGpuBenchmark.h
M libc/src/__support/OSUtil/baremetal/io.cpp
M libc/src/__support/OSUtil/baremetal/io.h
M libc/test/UnitTest/LibcTest.cpp
M libc/test/src/__support/CPP/type_traits_test.cpp
M libc/test/src/__support/FPUtil/fpbits_test.cpp
M libc/test/src/__support/big_int_test.cpp
M libc/test/src/math/RoundToIntegerTest.h
M libc/test/src/math/smoke/FMaxTest.h
M libc/test/src/math/smoke/FMaximumMagNumTest.h
M libc/test/src/math/smoke/FMaximumMagTest.h
M libc/test/src/math/smoke/FMaximumNumTest.h
M libc/test/src/math/smoke/FMaximumTest.h
M libc/test/src/math/smoke/FMinTest.h
M libc/test/src/math/smoke/FMinimumMagNumTest.h
M libc/test/src/math/smoke/FMinimumMagTest.h
M libc/test/src/math/smoke/FMinimumNumTest.h
M libc/test/src/math/smoke/FMinimumTest.h
M libc/test/src/math/smoke/FModTest.h
M libc/test/src/math/smoke/FrexpTest.h
M libc/test/src/math/smoke/ILogbTest.h
M libc/test/src/math/smoke/LogbTest.h
M libc/test/src/stdio/sprintf_test.cpp
M libc/test/src/string/memory_utils/op_tests.cpp
M libcxx/docs/FeatureTestMacroTable.rst
M libcxx/docs/ReleaseNotes/19.rst
M libcxx/docs/Status/Cxx2cPapers.csv
M libcxx/include/__mdspan/extents.h
M libcxx/include/barrier
M libcxx/include/future
M libcxx/include/ios
M libcxx/include/latch
M libcxx/include/locale
M libcxx/include/locale.h
M libcxx/include/mdspan
M libcxx/include/regex
M libcxx/include/semaphore
M libcxx/include/shared_mutex
M libcxx/include/stop_token
M libcxx/include/thread
M libcxx/include/version
A libcxx/test/std/containers/views/mdspan/extents/dims.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/mdspan.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp
M libcxx/utils/generate_feature_test_macro_components.py
M lld/test/ELF/systemz-gotent-relax-und-dso.s
M lld/test/ELF/systemz-gotent-relax.s
M lld/test/ELF/systemz-init-padding.s
M lld/test/ELF/systemz-plt.s
M lldb/include/lldb/API/SBValue.h
M lldb/source/API/SBValue.cpp
M lldb/test/API/python_api/formatters/TestFormattersSBAPI.py
M lldb/test/API/python_api/formatters/main.cpp
M lldb/test/API/python_api/formatters/synth.py
M llvm/include/llvm/ADT/ArrayRef.h
M llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
A llvm/include/llvm/CodeGen/MachineVerifier.h
M llvm/include/llvm/CodeGen/SDPatternMatch.h
A llvm/include/llvm/CodeGen/TwoAddressInstructionPass.h
M llvm/include/llvm/IR/Instruction.h
M llvm/include/llvm/IR/IntrinsicsRISCVXCV.td
M llvm/include/llvm/IR/PatternMatch.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/include/llvm/Passes/StandardInstrumentations.h
M llvm/include/llvm/TargetParser/RISCVTargetParser.h
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
M llvm/lib/IR/Metadata.cpp
M llvm/lib/Linker/IRMover.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/StandardInstrumentations.cpp
M llvm/lib/Support/Unix/Path.inc
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.h
M llvm/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp
M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
M llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp
M llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp
M llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
M llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZInstrFormats.td
M llvm/lib/Target/SystemZ/SystemZInstrInfo.td
M llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
M llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
M llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
M llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
M llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
M llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/TargetParser/RISCVTargetParser.cpp
M llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
M llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
M llvm/lib/Transforms/Scalar/Reassociate.cpp
M llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp
M llvm/lib/Transforms/Utils/InlineFunction.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-concat-vectors.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir
M llvm/test/CodeGen/AArch64/concat-vector.ll
M llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll
M llvm/test/CodeGen/AArch64/itofp.ll
M llvm/test/CodeGen/AArch64/statepoint-twoaddr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/twoaddr-extract-dyn-v7f64.mir
M llvm/test/CodeGen/AMDGPU/amdgpu-late-codegenprepare.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
M llvm/test/CodeGen/AMDGPU/early-lis-two-address-partial-def.mir
M llvm/test/CodeGen/AMDGPU/fix-wwm-vgpr-copy.ll
M llvm/test/CodeGen/AMDGPU/gfx10-twoaddr-fma.mir
M llvm/test/CodeGen/AMDGPU/gfx11-twoaddr-fma.mir
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/global_atomic_optimizer_fp_rtn.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_optimizer_fp_no_rtn.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/twoaddr-fma-f64.mir
M llvm/test/CodeGen/AMDGPU/twoaddr-fma.mir
M llvm/test/CodeGen/AMDGPU/twoaddr-mad.mir
M llvm/test/CodeGen/AMDGPU/twoaddr-wmma.mir
M llvm/test/CodeGen/AMDGPU/verifier-sdwa-cvt.mir
M llvm/test/CodeGen/AMDGPU/verify-constant-bus-violations.mir
M llvm/test/CodeGen/AMDGPU/verify-ds-gws-align.mir
M llvm/test/CodeGen/AMDGPU/verify-duplicate-literal.mir
M llvm/test/CodeGen/AMDGPU/verify-gfx90a-aligned-vgprs.mir
M llvm/test/CodeGen/AMDGPU/verify-image-vaddr-align.mir
M llvm/test/CodeGen/AMDGPU/verify-image.mir
M llvm/test/CodeGen/AMDGPU/verify-scalar-store.mir
M llvm/test/CodeGen/AMDGPU/verify-sop.mir
M llvm/test/CodeGen/AMDGPU/verify-vimage-vsample.mir
M llvm/test/CodeGen/AMDGPU/verify-vopd-gfx12.mir
M llvm/test/CodeGen/AMDGPU/verify-vopd.mir
M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
M llvm/test/CodeGen/Hexagon/two-addr-tied-subregs.mir
A llvm/test/CodeGen/LoongArch/typepromotion-overflow.ll
M llvm/test/CodeGen/MIR/Generic/dbg-value-missing-loc.mir
M llvm/test/CodeGen/MIR/X86/dbg-value-list.mir
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
M llvm/test/CodeGen/RISCV/verify-instr.mir
A llvm/test/CodeGen/RISCV/xcvmac.ll
A llvm/test/CodeGen/SystemZ/vec-cmp-08.ll
M llvm/test/CodeGen/X86/combine-shl.ll
M llvm/test/CodeGen/X86/combine-srl.ll
M llvm/test/CodeGen/X86/distancemap.mir
A llvm/test/CodeGen/X86/huge-stack.ll
M llvm/test/CodeGen/X86/statepoint-vreg-twoaddr.mir
M llvm/test/CodeGen/X86/twoaddr-mul2.mir
M llvm/test/MC/Disassembler/SystemZ/insns.txt
M llvm/test/MC/SystemZ/insn-good-z15.s
M llvm/test/MC/SystemZ/insn-good-z196.s
M llvm/test/MC/SystemZ/insn-good-zEC12.s
M llvm/test/MC/SystemZ/insn-good.s
M llvm/test/TableGen/riscv-target-def.td
M llvm/test/Transforms/EarlyCSE/math-2.ll
M llvm/test/Transforms/InstSimplify/and-or-implied-cond.ll
M llvm/test/Transforms/InstSimplify/ptrtoint.ll
M llvm/test/Transforms/LoopStrengthReduce/RISCV/lsr-drop-solution.ll
A llvm/test/Transforms/LoopStrengthReduce/X86/preserving-debugloc-phi-binop.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-live-out-pointer-induction.ll
A llvm/test/Transforms/LoopVectorize/X86/divs-with-tail-folding.ll
M llvm/test/Transforms/LoopVectorize/X86/ephemeral-recipes.ll
A llvm/test/Transforms/LoopVectorize/X86/iv-live-outs.ll
M llvm/test/Transforms/LoopVectorize/X86/pointer-runtime-checks-unprofitable.ll
M llvm/test/Transforms/LoopVectorize/iv_outside_user.ll
M llvm/test/Transforms/LoopVectorize/no-fold-tail-by-masking-iv-external-uses.ll
M llvm/test/Transforms/LoopVectorize/pr58811-scev-expansion.ll
M llvm/test/Transforms/LoopVectorize/pr59319-loop-access-info-invalidation.ll
M llvm/test/Transforms/MemCpyOpt/memcpy-zero-size.ll
M llvm/test/Transforms/MemCpyOpt/memset-memcpy-dbgloc.ll
M llvm/test/Transforms/MemCpyOpt/memset-memcpy-redundant-memset.ll
M llvm/test/Transforms/MemCpyOpt/opaque-ptr.ll
A llvm/test/Transforms/SLPVectorizer/X86/select-reduction-op.ll
A llvm/test/Transforms/SimpleLoopUnswitch/preserving-dropping-debugloc-nontrivial.ll
M llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll
A llvm/test/tools/llvm-split/AMDGPU/declarations.ll
M llvm/tools/llc/NewPMDriver.cpp
M llvm/unittests/IR/PatternMatch.cpp
M llvm/utils/TableGen/DecoderEmitter.cpp
M llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
M llvm/utils/gn/secondary/clang/lib/AST/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/Sema/BUILD.gn
M mlir/docs/DialectConversion.md
M mlir/include/mlir/Dialect/Bufferization/Transforms/Passes.h
M mlir/include/mlir/Dialect/Linalg/IR/LinalgNamedStructuredOps.yaml
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/include/mlir/Dialect/SCF/TransformOps/SCFTransformOps.td
M mlir/include/mlir/Transforms/DialectConversion.h
M mlir/lib/Conversion/BufferizationToMemRef/BufferizationToMemRef.cpp
M mlir/lib/Conversion/LLVMCommon/TypeConverter.cpp
M mlir/lib/Dialect/Bufferization/Transforms/LowerDeallocations.cpp
M mlir/lib/Dialect/SCF/TransformOps/CMakeLists.txt
M mlir/lib/Dialect/SCF/TransformOps/SCFTransformOps.cpp
M mlir/lib/IR/AffineExpr.cpp
M mlir/lib/Transforms/Utils/DialectConversion.cpp
M mlir/python/mlir/dialects/linalg/opdsl/lang/comprehension.py
M mlir/python/mlir/dialects/linalg/opdsl/ops/core_named_ops.py
M mlir/test/Conversion/FuncToLLVM/func-memref-return.mlir
M mlir/test/Dialect/Bufferization/Transforms/lower-deallocations.mlir
M mlir/test/Dialect/Vector/vector-transfer-collapse-inner-most-dims.mlir
M mlir/test/Integration/GPU/CUDA/async.mlir
M mlir/test/Integration/GPU/ROCM/gpu-to-hsaco.mlir
M mlir/test/Integration/GPU/ROCM/printf.mlir
M mlir/test/Integration/GPU/ROCM/two-modules.mlir
M mlir/test/Integration/GPU/ROCM/vecadd.mlir
M mlir/test/Integration/GPU/ROCM/vector-transferops.mlir
A mlir/test/Transforms/test-block-legalization.mlir
M mlir/unittests/IR/AffineExprTest.cpp
M offload/test/api/omp_dynamic_shared_memory_amdgpu.c
M offload/test/api/omp_dynamic_shared_memory_mixed_amdgpu.c
M offload/test/offloading/bug51781.c
M offload/test/offloading/bug51982.c
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
fix typo
Created using spr 1.3.5-bogner
Compare: https://github.com/llvm/llvm-project/compare/a7e188949b0d...fd9bdead23e1
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