[all-commits] [llvm/llvm-project] d5f4f0: [RISCV] Always expand zero strided vp.strided.load...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d5f4f084d29ce95fa27e5b7e80a630ae194df4bb
      https://github.com/llvm/llvm-project/commit/d5f4f084d29ce95fa27e5b7e80a630ae194df4bb
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-07-15 (Mon, 15 Jul 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
    M llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll

  Log Message:
  -----------
  [RISCV] Always expand zero strided vp.strided.load (#98901)

This patch makes zero strided VP loads always be expanded to a scalar
load and splat even if +optimized-zero-stride-load is present.

Expanding it allows more .vx splat patterns to be matched, which is
needed to prevent regressions in #98111.

If the feature is present, RISCVISelDAGToDAG will combine it back to a
zero strided load.

The RV32 test diff also shows how need to emit a zero strided load
either way after expanding an SEW=64 strided load. We could maybe fix
this in a later patch by not doing the expand if SEW>XLEN.



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