[all-commits] [llvm/llvm-project] e4ee9b: [RISCV] Custom legalize vXf16 BUILD_VECTOR without...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e4ee9bf0d2dee8064c539c047ee525e5b7ad44e5
      https://github.com/llvm/llvm-project/commit/e4ee9bf0d2dee8064c539c047ee525e5b7ad44e5
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-07-07 (Sun, 07 Jul 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll

  Log Message:
  -----------
  [RISCV] Custom legalize vXf16 BUILD_VECTOR without Zfhmin. (#97874)

If we don't have Zfhmin, we will call `SoftPromoteHalfOperand` on the
BUILD_VECTOR. This operation is not supported by the generic code.

Instead, custom lower to a vXi16 BUILD_VECTOR using bitcasts.

Fixes #97849.



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