[all-commits] [llvm/llvm-project] 6337fd: [RISCV] Use EXTLOAD in lowerVECTOR_SHUFFLE. (#97862)

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6337fdcc520e8f948bef23b361c75edeb32ed015
      https://github.com/llvm/llvm-project/commit/6337fdcc520e8f948bef23b361c75edeb32ed015
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-07-05 (Fri, 05 Jul 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll

  Log Message:
  -----------
  [RISCV] Use EXTLOAD in lowerVECTOR_SHUFFLE. (#97862)

We're creating a load and a splat. The splat doesn't use the extended
bits so it doesn't matter what extend we use.



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