[all-commits] [llvm/llvm-project] f92bfc: [AArch64] All bits of an exact right shift are dem...

[Momchil Velikov via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f92bfca9fc217cad9026598ef6755e711c0be070
      https://github.com/llvm/llvm-project/commit/f92bfca9fc217cad9026598ef6755e711c0be070
  Author: Momchil Velikov <momchil.velikov at arm.com>
  Date:   2024-07-05 (Fri, 05 Jul 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    A llvm/test/CodeGen/AArch64/shr-exact-demanded-bits.ll

  Log Message:
  -----------
  [AArch64] All bits of an exact right shift are demanded (#97448)

When building a vector which contains zero elements, the AArch64 ISel
replaces those elements with `undef`, if they are right shifted out.

However, these elements need to stay zero if the right shift is exact,
or otherwise we will be introducing undefined behavior.

Should allow https://github.com/llvm/llvm-project/pull/92528 to be
recommitted.



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