[all-commits] [llvm/llvm-project] 56f0ec: [RISCV] Implement Intrinsics Support for XCValu Ex...

[realqhc via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 56f0ecd6db9219b7d14a8eda613d6b75060643eb
      https://github.com/llvm/llvm-project/commit/56f0ecd6db9219b7d14a8eda613d6b75060643eb
  Author: realqhc <caiqihan021 at hotmail.com>
  Date:   2024-07-04 (Thu, 04 Jul 2024)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCVXCV.td
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
    A llvm/test/CodeGen/RISCV/xcvalu.ll

  Log Message:
  -----------
  [RISCV] Implement Intrinsics Support for XCValu Extension in CV32E40P (#85603)

Implement XCValu intrinsics for CV32E40P according to the specification.

This commit is part of a patch-set to upstream the vendor specific
extensions of CV32E40P that need LLVM intrinsics to implement Clang
builtins.

Contributors: @CharKeaney, @ChunyuLiao, @jeremybennett, @lewis-revill,
@NandniJamnadas, @PaoloS02, @serkm, @simonpcook, @xingmingjie.



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