[all-commits] [llvm/llvm-project] e860c1: [Docs][RISCV] Document RISC-V vector codegen (#96740)

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e860c166556105c6f9275e130a0c27ae117a5f12
      https://github.com/llvm/llvm-project/commit/e860c166556105c6f9275e130a0c27ae117a5f12
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-07-03 (Wed, 03 Jul 2024)

  Changed paths:
    A llvm/docs/RISCV/RISCVVectorExtension.rst
    M llvm/docs/UserGuides.rst

  Log Message:
  -----------
  [Docs][RISCV] Document RISC-V vector codegen (#96740)

This is a revival of https://reviews.llvm.org/D142348, and attempts to
document how RVV semantics can be expressed in LLVM IR as well as how
codegen works in the backend.

Parts of this are taken from the original RFC
https://lists.llvm.org/pipermail/llvm-dev/2020-October/145850.html, but
I've largely rewritten this from the original differential revision to
exclude explaining the specification itself and instead just focus on
the LLVM specific bits. (I figured that there's better material
available elsewhere for learning about RVV itself)

I've also updated it to include as much as I know about fixed vector
codegen as well as the recent changes to vsetvli insertion.



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