[all-commits] [llvm/llvm-project] 93e0ff: [lld] Add `--lto-emit-asm` and alias `--plugin-opt...

Tue Jul 2 15:17:53 PDT 2024

  Branch: refs/heads/users/MaskRay/spr/mc-dont-treat-altentry-symbols-as-atoms
  Home:   https://github.com/llvm/llvm-project
  Commit: 93e0ffa790c5f738171ed90004ab2b9e46f8d387
      https://github.com/llvm/llvm-project/commit/93e0ffa790c5f738171ed90004ab2b9e46f8d387
  Author: Joseph Huber <huberjn at outlook.com>
  Date:   2024-07-02 (Tue, 02 Jul 2024)

  Changed paths:
    M lld/ELF/Driver.cpp
    M lld/ELF/Options.td
    M lld/test/ELF/lto/emit-llvm.ll

  Log Message:
  -----------
  [lld] Add `--lto-emit-asm` and alias `--plugin-opt=emit-llvm` to it (#97469)

Summary:
The LTO pass currently supporting emitting LTO via the
`--plugin-opt=emit-llvm` option. However, there is a very similar option
called `--lto-emit-asm`. This patch just makes the usage more
consistent and more obvious that emitting LLVM-IR is supported.

  Commit: 2ee86a1ebb9be7ff7be893b411a4af0a1dcee420
      https://github.com/llvm/llvm-project/commit/2ee86a1ebb9be7ff7be893b411a4af0a1dcee420
  Author: Tim Gymnich <tgymnich at icloud.com>
  Date:   2024-07-02 (Tue, 02 Jul 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
    M llvm/test/CodeGen/AArch64/popcount.ll

  Log Message:
  -----------
  [AArch64][GlobalISel] Improve non-SVE popcount for 32bit and 64 bit using udot (#96409)

Follow up for #95881

Use udot instead of a sequence of uaddlp instructions when summing up
lanes for popcount.

  Commit: 9fa7f401b2651663407562932529f72142bf8aaa
      https://github.com/llvm/llvm-project/commit/9fa7f401b2651663407562932529f72142bf8aaa
  Author: alx32 <103613512+alx32 at users.noreply.github.com>
  Date:   2024-07-02 (Tue, 02 Jul 2024)

  Changed paths:
    M lld/MachO/ObjC.cpp
    A lld/test/MachO/objc-category-merging-swift.s

  Log Message:
  -----------
  [lld-macho]  Category merger: handle addends when getting symbol at offset (#91238)

Currently the `tryFindDefinedOnIsec` takes in an `InputSection` and an
`offset` and is supposed to return the target symbol that is referenced
on that `InputSection` at the given offset.

However, it does not deal with the reloc `addend` and might return the
incorrect symbol.
Here we add support for handling the reloc's `addend`.

  Commit: 1490141145db1f9136a16bbce0f020e576613a72
      https://github.com/llvm/llvm-project/commit/1490141145db1f9136a16bbce0f020e576613a72
  Author: Fangrui Song <i at maskray.me>
  Date:   2024-07-02 (Tue, 02 Jul 2024)

  Changed paths:
    M llvm/include/llvm/MC/MCSection.h
    M llvm/include/llvm/MC/MCSectionMachO.h
    M llvm/lib/MC/MachObjectWriter.cpp

  Log Message:
  -----------
  Move MCSection::LayoutOrder to MCSectionMachO

This variable is similar to `Ordinal` but only used for Mach-O to place
zerofill sections ("virtual sections" in MC term) after non-zerofill ones.

Follow-up to 7840c0066837797cdeb62aab63044b964aa7f372.

Pull Request: https://github.com/llvm/llvm-project/pull/97474

  Commit: 45507166a1b38ce2831bd1e32f43977f647ccf47
      https://github.com/llvm/llvm-project/commit/45507166a1b38ce2831bd1e32f43977f647ccf47
  Author: Igor Kudrin <ikudrin at accesssoftek.com>
  Date:   2024-07-02 (Tue, 02 Jul 2024)

  Changed paths:
    M llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-cfi.ll
    M llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-diff-scope-same-key.ll
    M llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-non-leaf.ll
    M llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-regsave.mir
    M llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-same-scope-diff-key.ll
    M llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-same-scope-same-key-a.ll
    M llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-same-scope-same-key-b.ll
    M llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-subtarget.ll
    M llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-thunk.ll
    M llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-v8-3.ll

  Log Message:
  -----------
  [AArch64][MachineOutliner][NFC] Re-enable some tests (#96376)

Part of the tests did not run and some checks were missing due to
incorrect prefixes. The patch also updates the check lines to catch up
with recent changes.

The problematic revisions were:
 * [D70635](https://reviews.llvm.org/D70635)
 * [D71658](https://reviews.llvm.org/D71658)
 * [D111780](https://reviews.llvm.org/D111780)

  Commit: 79516ddbee3a1d6c95cfbe6d14c790f741167165
      https://github.com/llvm/llvm-project/commit/79516ddbee3a1d6c95cfbe6d14c790f741167165
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2024-07-02 (Tue, 02 Jul 2024)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
    M llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll

  Log Message:
  -----------
  AMDGPU: Fix assert from wrong address space size assumption (#97267)

This was assuming the source address space was at least as large
as the destination of the cast. I'm not sure why this was casting
to begin with; the assumption seems to be the source
address space from the root addrspacecast matches the underlying
object so directly check that.

Fixes #97457

  Commit: 57555c6a0a96790bf1408b056405abe07899ead4
      https://github.com/llvm/llvm-project/commit/57555c6a0a96790bf1408b056405abe07899ead4
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-07-02 (Tue, 02 Jul 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  Log Message:
  -----------
  [RISCV] Don't custom lower f16 SCALAR_TO_VECTOR with Zvfhmin.

This doesn't appear to be tested and our custom handler doesn't
support this right now.

  Commit: ac85e308fcb660970409702636716f4ee8dbb709
      https://github.com/llvm/llvm-project/commit/ac85e308fcb660970409702636716f4ee8dbb709
  Author: Fangrui Song <i at maskray.me>
  Date:   2024-07-02 (Tue, 02 Jul 2024)

  Changed paths:
    M lld/ELF/Driver.cpp
    M lld/ELF/Options.td
    M lld/MachO/ObjC.cpp
    M lld/test/ELF/lto/emit-llvm.ll
    A lld/test/MachO/objc-category-merging-swift.s
    M llvm/include/llvm/MC/MCSection.h
    M llvm/include/llvm/MC/MCSectionMachO.h
    M llvm/lib/MC/MachObjectWriter.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-cfi.ll
    M llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-diff-scope-same-key.ll
    M llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-non-leaf.ll
    M llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-regsave.mir
    M llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-same-scope-diff-key.ll
    M llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-same-scope-same-key-a.ll
    M llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-same-scope-same-key-b.ll
    M llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-subtarget.ll
    M llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-thunk.ll
    M llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-v8-3.ll
    M llvm/test/CodeGen/AArch64/popcount.ll
    M llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll

  Log Message:
  -----------
  better description

Created using spr 1.3.5-bogner

Compare: https://github.com/llvm/llvm-project/compare/631058bba0a6...ac85e308fcb6

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