[all-commits] [llvm/llvm-project] 7e6e49: [RISCV] Use EXTLOAD instead of ZEXTLOAD when lower...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7e6e4986e64e8528c149d3ba90188248e2f2013c
      https://github.com/llvm/llvm-project/commit/7e6e4986e64e8528c149d3ba90188248e2f2013c
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-07-01 (Mon, 01 Jul 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll

  Log Message:
  -----------
  [RISCV] Use EXTLOAD instead of ZEXTLOAD when lowering riscv_masked_strided_load with zero stride. (#97317)

The splat we generate after the load doesn't use the extended bits, so it
shouldn't matter which extend type we use.

EXTLOAD is lowered as SEXTLOAD on every element type except i8.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications