[all-commits] [llvm/llvm-project] 2dbd19: DAG/GlobalISel: Set disjoint for or in copysign lo...

[Matt Arsenault via All-commits]

  Branch: refs/heads/users/arsenm/dag-set-disjoint-on-lowered-copysign
  Home:   https://github.com/llvm/llvm-project
  Commit: 2dbd199ac39463696a7e96e2eefa500f7fdc29ed
      https://github.com/llvm/llvm-project/commit/2dbd199ac39463696a7e96e2eefa500f7fdc29ed
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2024-06-28 (Fri, 28 Jun 2024)

  Changed paths:
    M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-fcopysign.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir

  Log Message:
  -----------
  DAG/GlobalISel: Set disjoint for or in copysign lowering

We masked out the sign bit from one value, and the non-sign bits
from the other so there should be no common bits set.

No idea how to test this on the DAG path, other than scraping
the debug logs. A few targets hit this path with f16 values, but
the resulting i16 ors get anyext promoted and lose the disjoint
flag. In the fp128 case, PPC gets further and the or loses the flag
somewhere else later. Adding a haveNoCommonBits assert shows this
works though.



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