[all-commits] [llvm/llvm-project] cad726: [RISCV] Support zext.h mnemonic with Zbkb. (#96821)

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: cad72632eb0d612fe18c38ac4526d80a6b800f96
      https://github.com/llvm/llvm-project/commit/cad72632eb0d612fe18c38ac4526d80a6b800f96
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-06-27 (Thu, 27 Jun 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
    M llvm/test/CodeGen/RISCV/rv32zbkb.ll
    M llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbkb.ll
    M llvm/test/CodeGen/RISCV/rv64zbkb.ll
    M llvm/test/MC/RISCV/rv32zbkb-only-valid.s
    M llvm/test/MC/RISCV/rv32zbkb-valid.s
    M llvm/test/MC/RISCV/rv64zbkb-valid.s

  Log Message:
  -----------
  [RISCV] Support zext.h mnemonic with Zbkb. (#96821)

Zbkb adds generic pack insructions. The zext.h encodings from Zbb are
subsets of the generic encodings with rs2=x0. zext.h is pack on RV32 and
packw on RV64.

Previously we only supported zext.h as a single instruction mnemonic in
the assembler when Zbb was enabled. Otherwise we would emit it as 2
shifts. This patches recognizes it when either Zbkb or Zbb is enabled.

This patch also enables the zext.h isel patterns when Zbkb is enabled
without Zbb.



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