[all-commits] [llvm/llvm-project] 15fc80: [X86][CodeGen] Support hoisting load/store with co...

[Shengchen Kan via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 15fc801cf0ca7a4d09fe52546394efa51414047a
      https://github.com/llvm/llvm-project/commit/15fc801cf0ca7a4d09fe52546394efa51414047a
  Author: Shengchen Kan <shengchen.kan at intel.com>
  Date:   2024-06-27 (Thu, 27 Jun 2024)

  Changed paths:
    M llvm/include/llvm/Analysis/TargetTransformInfo.h
    M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
    M llvm/include/llvm/CodeGen/TargetLowering.h
    M llvm/lib/Analysis/TargetTransformInfo.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/lib/Target/X86/X86ISelLowering.h
    M llvm/lib/Target/X86/X86InstrCMovSetCC.td
    M llvm/lib/Target/X86/X86InstrFragments.td
    M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
    M llvm/lib/Target/X86/X86TargetTransformInfo.h
    A llvm/test/CodeGen/X86/apx/cf.ll

  Log Message:
  -----------
  [X86][CodeGen] Support hoisting load/store with conditional faulting (#96720)

1. Add TTI interface for conditional load/store.
2. Mark 1 x i16/i32/i64 masked load/store legal so that it's not
   legalized in pass scalarize-masked-mem-intrin.
3. Visit 1 x i16/i32/i64 masked load/store to build a target-specific
   CLOAD/CSTORE node to avoid error in
   `DAGTypeLegalizer::ScalarizeVectorResult`.
4. Combine DAG to simplify the nodes for CLOAD/CSTORE.
5. Lower CLOAD/CSTORE to CFCMOV by pattern match.

This is CodeGen part of #95515



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