[all-commits] [llvm/llvm-project] 04c278: [MC, COFF] Change how we handle section symbols
shaw young via All-commits
all-commits at lists.llvm.org
Wed Jun 26 13:44:53 PDT 2024
Branch: refs/heads/users/shawbyoung/spr/bolt-hash-based-function-matching-1
Home: https://github.com/llvm/llvm-project
Commit: 04c27852e47093f7efa18609dbf57b3ce58a3ffa
https://github.com/llvm/llvm-project/commit/04c27852e47093f7efa18609dbf57b3ce58a3ffa
Author: Fangrui Song <i at maskray.me>
Date: 2024-06-25 (Tue, 25 Jun 2024)
Changed paths:
M llvm/include/llvm/MC/MCContext.h
M llvm/include/llvm/MC/MCWinCOFFStreamer.h
M llvm/lib/MC/MCContext.cpp
M llvm/lib/MC/MCObjectFileInfo.cpp
M llvm/lib/MC/MCWinCOFFStreamer.cpp
M llvm/lib/MC/WinCOFFObjectWriter.cpp
M llvm/test/DebugInfo/X86/InlinedFnLocalVar.ll
M llvm/test/DebugInfo/X86/ref_addr_relocation.ll
M llvm/test/ExecutionEngine/RuntimeDyld/X86/COFF_x86_64.s
M llvm/test/MC/COFF/section-comdat-conflict.s
M llvm/test/MC/COFF/section-comdat.s
A llvm/test/MC/COFF/section-sym-err.s
Log Message:
-----------
[MC,COFF] Change how we handle section symbols
13a79bbfe583e1d8cc85d241b580907260065eb8 (2017) unified `BeginSymbol` and
section symbol for ELF. This patch does the same for COFF.
* In getCOFFSection, all sections now have a `BeginSymbol` (section
symbol). We do not need a dummy symbol name when `getBeginSymbol` is
needed (used by AsmParser::Run and DWARF generation).
* Section symbols are in the global symbol table. `call .text` will
reference the section symbol instead of an undefined symbol. This
matches GNU assembler. Unlike GNU, redefining the section symbol will
cause a "symbol 'foo0' is already defined" error (see
`section-sym-err.s`).
Pull Request: https://github.com/llvm/llvm-project/pull/96459
Commit: d26451411f9cab2200a749f5b7a2f4f93c154445
https://github.com/llvm/llvm-project/commit/d26451411f9cab2200a749f5b7a2f4f93c154445
Author: Akshay Deodhar <adeodhar at nvidia.com>
Date: 2024-06-25 (Tue, 25 Jun 2024)
Changed paths:
M llvm/test/CodeGen/NVPTX/f16-instructions.ll
Log Message:
-----------
Enforce parameter order in f16 call, flipped call unit tests (#96258)
Commit: 0280f97b36c83a7129e5dbce53c603b7ec5d82fe
https://github.com/llvm/llvm-project/commit/0280f97b36c83a7129e5dbce53c603b7ec5d82fe
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-06-25 (Tue, 25 Jun 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/insertelement-uses-vectorized-index.ll
Log Message:
-----------
[SLP]Fix PR95925: extract vectorized index of the potential buildvector sequence.
If the vectorized scalar is not the insert value in the buildvector
sequence but the index, it should be always extracted.
Commit: dff6871cdbce8569a141d541023061294860fb95
https://github.com/llvm/llvm-project/commit/dff6871cdbce8569a141d541023061294860fb95
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-06-25 (Tue, 25 Jun 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-constant-f16.mir
Log Message:
-----------
[RISCV][GISel] Support G_FCONSTANT for Zfh.
Commit: 7e59b20034aa77d69e5218ff44e3cba8a500f76a
https://github.com/llvm/llvm-project/commit/7e59b20034aa77d69e5218ff44e3cba8a500f76a
Author: vaibhav <73255802+mrdaybird at users.noreply.github.com>
Date: 2024-06-25 (Tue, 25 Jun 2024)
Changed paths:
M llvm/lib/Analysis/ScalarEvolution.cpp
A llvm/test/Analysis/ScalarEvolution/pr92560.ll
Log Message:
-----------
[SCEV] Support addrec in right hand side in howManyLessThans (#92560)
Fixes #92554 (std::reverse will auto-vectorize now)
When calculating number of times a exit condition containing a
comparison is executed, we mostly assume that RHS of comparison should
be loop invariant, but it may be another add-recurrence.
~In that case, we can try the computation with `LHS = LHS - RHS` and
`RHS = 0`.~ (It is not valid unless proven that it doesn't wrap)
**Edit:**
We can calculate back edge count for loop structure like:
```cpp
left = left_start
right = right_start
while(left < right){
// ...do something...
left += s1; // the stride of left is s1 (> 0)
right -= s2; // the stride of right is -s2 (s2 > 0)
}
// left and right converge somewhere in the middle of their start values
```
We can calculate the backedge-count as ceil((End - left_start) /u (s1-
(-s2)) where, End = max(left_start, right_start).
**Alive2**: https://alive2.llvm.org/ce/z/ggxx58
Commit: edf5782f1780f480c3ae3fc0a44bf5432f9aa48b
https://github.com/llvm/llvm-project/commit/edf5782f1780f480c3ae3fc0a44bf5432f9aa48b
Author: Jason Eckhardt <jeckhardt at nvidia.com>
Date: 2024-06-25 (Tue, 25 Jun 2024)
Changed paths:
A llvm/test/TableGen/check-duplicate-tuple-regs.td
M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
Log Message:
-----------
[TableGen] Check for duplicate register tuple definitions. (#95725)
Currently TableGen does not directly detect duplicate synthesized
registers as can happen in this example:
def GPR128 : RegisterTuples<[sub0, sub1, sub2, sub3],
[(decimate (shl GPR32, 0), 1),
(decimate (shl GPR32, 1), 1),
(decimate (shl GPR32, 2), 1),
(decimate (shl GPR32, 3), 1)]>;
def GPR128_Aligned : RegisterTuples<[sub0, sub1, sub2, sub3],
[(decimate (shl GPR32, 0), 4),
(decimate (shl GPR32, 1), 4),
(decimate (shl GPR32, 2), 4),
(decimate (shl GPR32, 3), 4)]>;
TableGen does fail, but with an unrelated and difficult to understand
error that happens downstream of tuple expansion:
"error: No SubRegIndex for R0_R1_R2_R3 in R0_R1_R2_R3".
This patch detects the problem directly during expansion and emits an
error pointing the user to the actual issue:
"error: Register tuple redefines register 'R0_R1_R2_R3'".
Commit: 8bba070ef84ce41be4d3ec0b87d85a1be62325b0
https://github.com/llvm/llvm-project/commit/8bba070ef84ce41be4d3ec0b87d85a1be62325b0
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-06-25 (Tue, 25 Jun 2024)
Changed paths:
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
Log Message:
-----------
AMDGPU: Expand testing of atomicrmw fmin/fmax lowering
Cover amdgpu.no.fine.grained.memory vs. amdgpu.no.remote.memory.
Commit: 4f80f362a5b2b0339bf702f6ff7ae14304c76185
https://github.com/llvm/llvm-project/commit/4f80f362a5b2b0339bf702f6ff7ae14304c76185
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-06-25 (Tue, 25 Jun 2024)
Changed paths:
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
Log Message:
-----------
AMDGPU: Add new metadata and expand atomicrmw fadd expansion tests
Commit: e214ed9d7060f6caa0c1bb756edb62643f23aa5b
https://github.com/llvm/llvm-project/commit/e214ed9d7060f6caa0c1bb756edb62643f23aa5b
Author: Nick Desaulniers (paternity leave) <nickdesaulniers at users.noreply.github.com>
Date: 2024-06-25 (Tue, 25 Jun 2024)
Changed paths:
M libc/config/linux/arm/entrypoints.txt
Log Message:
-----------
[libc][arm] move setjmp+longjmp to fullbuild-only entrypoints (#96708)
The opaque type jmp_buf should only be tested in fullbuild mode.
Commit: 847235bbef153c6d805d415cea8494297eaf2bdb
https://github.com/llvm/llvm-project/commit/847235bbef153c6d805d415cea8494297eaf2bdb
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-06-25 (Tue, 25 Jun 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rv32zbb.ll
M llvm/test/CodeGen/RISCV/rv64zbb.ll
Log Message:
-----------
[RISCV] Add DAG combine to turn (sub (shl X, 8), X) into orc.b (#96680)
If only bits 8, 16, 24, 32, etc. can be non-zero.
This is what (mul X, 255) is decomposed to. This decomposition happens
early before RISC-V DAG combine runs.
This patch does not support types larger than XLen so i64 on rv32 fails
to generate 2 orc.b instructions. It might have worked if the mul hadn't
been decomposed before it was expanded.
Partial fix for #96595.
Commit: 0d533665054c3a04681c46f3ed88960f28777be1
https://github.com/llvm/llvm-project/commit/0d533665054c3a04681c46f3ed88960f28777be1
Author: YunQiang Su <syq at debian.org>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/include/llvm/ADT/APFloat.h
M llvm/unittests/ADT/APFloatTest.cpp
Log Message:
-----------
APFloat: Add minimumnum and maximumnum (#96304)
They implements IEEE754-2019 minimumNumber and maximumNumber semantics.
Newer libc also has these 2 functions with names
fminimum_num
fmaximum_num
We are planning add minimumnum and maximumnum intrinsic. This is a step
to the goal.
Commit: 54ca5a800d12bf76dabc957163df02c3ea005627
https://github.com/llvm/llvm-project/commit/54ca5a800d12bf76dabc957163df02c3ea005627
Author: PiJoules <6019989+PiJoules at users.noreply.github.com>
Date: 2024-06-25 (Tue, 25 Jun 2024)
Changed paths:
M libc/src/__support/fixedvector.h
M libc/test/src/__support/fixedvector_test.cpp
Log Message:
-----------
[libc][fixedvector] Add const_iterator begin/end (#96714)
Commit: e6c2216940885ae5b0d6509dac73417c40d6c62f
https://github.com/llvm/llvm-project/commit/e6c2216940885ae5b0d6509dac73417c40d6c62f
Author: Haopeng Liu <153236845+haopliu at users.noreply.github.com>
Date: 2024-06-25 (Tue, 25 Jun 2024)
Changed paths:
M llvm/include/llvm/IR/ConstantRangeList.h
M llvm/lib/IR/ConstantRangeList.cpp
M llvm/unittests/IR/ConstantRangeListTest.cpp
Log Message:
-----------
Add ConstantRangeList::unionWith() and ::intersectWith() (#96547)
Add ConstantRangeList::unionWith() and ::intersectWith().
These methods will be used in the "initializes" attribute inference.
https://github.com/llvm/llvm-project/commit/df11106068294fb00f11988d3f48336e2cbed364
Commit: 6b29965fd9355243f23a83a590a70ac7744f0e0f
https://github.com/llvm/llvm-project/commit/6b29965fd9355243f23a83a590a70ac7744f0e0f
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M clang-tools-extra/clang-tidy/tool/run-clang-tidy.py
Log Message:
-----------
[clang-tidy] align all help message in run-clang-tidy (#96199)
Commit: ef864516f7d2f4e256f74570beec8f29905d8828
https://github.com/llvm/llvm-project/commit/ef864516f7d2f4e256f74570beec8f29905d8828
Author: Diego Caballero <dieg0ca6aller0 at gmail.com>
Date: 2024-06-25 (Tue, 25 Jun 2024)
Changed paths:
M .github/CODEOWNERS
Log Message:
-----------
[mlir] Remove `*` from generic Linalg/Vector rules in CODEOWNERS (#96581)
The PR removes the `*` from the generic MLIR Vector/Linalg rules. The
`*` symbol keeps the match local to the files in the directory,
excluding sub-directories, which was not the intention when I added
these rules.
Commit: a4fef26c7d13c003b253052fbe670af451f9f1ff
https://github.com/llvm/llvm-project/commit/a4fef26c7d13c003b253052fbe670af451f9f1ff
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/lib/Target/X86/X86FixupSetCC.cpp
A llvm/test/CodeGen/X86/apx/setzucc.ll
Log Message:
-----------
[X86][FixupSetCC] Substitute setcc + zext pair with setzucc if possible (#96594)
Commit: 55e60c35212e0cf293572499ee74e96438d64b99
https://github.com/llvm/llvm-project/commit/55e60c35212e0cf293572499ee74e96438d64b99
Author: dpalermo <dan.palermo at amd.com>
Date: 2024-06-25 (Tue, 25 Jun 2024)
Changed paths:
M flang/include/flang/Lower/BoxAnalyzer.h
Log Message:
-----------
[flang] Fix BoxAnalyzer.h for LLVM_ENABLE_EXPENSIVE_CHECKS (#96675)
Fixes assert seen trying to use default number of inlined elements for
`SmallVector<T>` but `sizeof(T)` is really big. Seen with
-DLLVM_ENABLE_EXPENSIVE_CHECKS.
Commit: 811e505c5b43242b20029cbd7a85d87763addf83
https://github.com/llvm/llvm-project/commit/811e505c5b43242b20029cbd7a85d87763addf83
Author: Hua Tian <akiratian at tencent.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/lib/CodeGen/WindowScheduler.cpp
M llvm/test/CodeGen/Hexagon/swp-ws-dead-def.mir
M llvm/test/CodeGen/Hexagon/swp-ws-exp-dbg.mir
M llvm/test/CodeGen/Hexagon/swp-ws-exp.mir
M llvm/test/CodeGen/Hexagon/swp-ws-fail-0.mir
M llvm/test/CodeGen/Hexagon/swp-ws-fail-1.mir
M llvm/test/CodeGen/Hexagon/swp-ws-fail-2.mir
A llvm/test/CodeGen/Hexagon/swp-ws-fail-3.mir
M llvm/test/CodeGen/Hexagon/swp-ws-meta-instr.mir
M llvm/test/CodeGen/Hexagon/swp-ws-phi.mir
M llvm/test/CodeGen/Hexagon/swp-ws-sqrt.mir
M llvm/test/CodeGen/Hexagon/swp-ws-weak-dep.mir
Log Message:
-----------
[llvm][CodeGen] Update checking method of loop-carried phi in window scheduler (#96288)
Added some logic to check loop-carried phis in the window scheduler. It now includes the scenario where the preceding phi uses the virtual register defined by the succeeding phi.
Commit: 0fe82ea2ea7c92388a33652997b98d159d253012
https://github.com/llvm/llvm-project/commit/0fe82ea2ea7c92388a33652997b98d159d253012
Author: Peter Collingbourne <peter at pcc.me.uk>
Date: 2024-06-25 (Tue, 25 Jun 2024)
Changed paths:
M llvm/utils/gn/secondary/compiler-rt/lib/hwasan/BUILD.gn
Log Message:
-----------
gn build: Add missing source files to hwasan library.
Commit: 96b1f8859df3c82b6362b1dd07ee485f48cb1816
https://github.com/llvm/llvm-project/commit/96b1f8859df3c82b6362b1dd07ee485f48cb1816
Author: Lang Hames <lhames at gmail.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/Core.h
M llvm/lib/ExecutionEngine/Orc/Core.cpp
Log Message:
-----------
[ORC] Remove redundant locking of session mutex, update method name.
JITDylib::removeTracker already runs with the session mutex locked (and must do
so), so remove the redundant locking and add an 'IL_' ("inside lock") prefix to
the method name.
Commit: 896dd322afcc1cf5dc4fa7375dedd55b59001eb4
https://github.com/llvm/llvm-project/commit/896dd322afcc1cf5dc4fa7375dedd55b59001eb4
Author: Lang Hames <lhames at gmail.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/ObjectLinkingLayer.cpp
Log Message:
-----------
[ORC] Fix block dependence calculation in ObjectLinkingLayer.
This fixes a bug in ObjectLinkingLayer::computeBlockNonLocalDeps: The worklist
needs to be built *after* all immediate dependencies / dependants are recorded,
rather than trying to populate it as part of the same loop. (Trying to do the
latter causes us to miss some blocks that should have been included in the
worklist).
This fixes a bug discovered by @Sahil123 on discord during work on
out-of-process execution support in the clang-repl.
No testcase yet. This *might* be testable with a unit test and a custom
JITLinkContext but I believe some aspects of the algorithm depend on memory
layout. I'll need to investigate that. Alternatively we could add llvm-jitlink
testcases that exercise concurrent linking (and should probably do that anyway).
Either option will require some investment and I don't want to hold this fix up
in the mean time.
Commit: b347a720bfc4dfd6ff16cfde54f9a56f00efdb3c
https://github.com/llvm/llvm-project/commit/b347a720bfc4dfd6ff16cfde54f9a56f00efdb3c
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
M llvm/test/Instrumentation/InstrProfiling/mcdc.ll
Log Message:
-----------
[MC/DC][Coverage] Make tvbitmapupdate capable of atomic write (#96042)
This also introduces "Test and conditional Read-Modify-Write". The flow
to `atomicrmw or` is marked as `unlikely`.
Commit: f71f95d6aa27057f4fc10695ee9c8eb1ec77b763
https://github.com/llvm/llvm-project/commit/f71f95d6aa27057f4fc10695ee9c8eb1ec77b763
Author: Fangrui Song <i at maskray.me>
Date: 2024-06-25 (Tue, 25 Jun 2024)
Changed paths:
M lld/ELF/InputSection.cpp
M lld/ELF/Relocations.cpp
M llvm/include/llvm/Object/ELFTypes.h
Log Message:
-----------
[ELF] Rename IsRela to HasAddend
`IsRela` is used by lld to differentiate REL and RELA static
relocations. The proposed CREL patch will reuse `IsRela` for CREL
(#91280). Rename `IsRela` to be more appropriate.
Pull Request: https://github.com/llvm/llvm-project/pull/96592
Commit: 174d3537c203ec81a6810bad554a5a71cc331e24
https://github.com/llvm/llvm-project/commit/174d3537c203ec81a6810bad554a5a71cc331e24
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/lib/Target/X86/X86FixupSetCC.cpp
Log Message:
-----------
[X86] Fix description for pass X86FixupSetCC.cpp, NFCI
It should be a typo when the author created this file from
X86OptimizeLEAs.cpp.
Commit: 21bfc0e8ed798f078d4e87e6f43af025f078ead3
https://github.com/llvm/llvm-project/commit/21bfc0e8ed798f078d4e87e6f43af025f078ead3
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/lib/Target/X86/X86FixupSetCC.cpp
Log Message:
-----------
Revert "[X86] Fix description for pass X86FixupSetCC.cpp, NFCI"
This reverts commit 174d3537c203ec81a6810bad554a5a71cc331e24.
It introduced new typo "IMul" by accident.
Commit: 9253ac24aac0198371260762838758f587fa3f9d
https://github.com/llvm/llvm-project/commit/9253ac24aac0198371260762838758f587fa3f9d
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/lib/Target/X86/X86FixupSetCC.cpp
Log Message:
-----------
[X86] Fix description for pass X86FixupSetCC.cpp, NFCI
It should be a typo when the author created this file from
X86OptimizeLEAs.cpp.
Commit: 89d8df12015ac3440190d372a8d439614027dc2c
https://github.com/llvm/llvm-project/commit/89d8df12015ac3440190d372a8d439614027dc2c
Author: pcc <peter at pcc.me.uk>
Date: 2024-06-25 (Tue, 25 Jun 2024)
Changed paths:
M clang/lib/CodeGen/CodeGenAction.cpp
M clang/test/CodeGen/asan-frame-pointer.cpp
M clang/test/CodeGen/asan-globals.cpp
A clang/test/CodeGen/coverage-target-attr.c
M clang/test/CodeGen/sanitize-metadata-nosanitize.c
M llvm/include/llvm/IR/Function.h
M llvm/include/llvm/IR/LLVMContext.h
M llvm/lib/IR/Function.cpp
M llvm/lib/IR/LLVMContext.cpp
M llvm/lib/IR/LLVMContextImpl.h
Log Message:
-----------
CodeGen, IR: Add target-{cpu,features} attributes to functions created via createWithDefaultAttr().
Functions created with createWithDefaultAttr() need to have the
correct target-{cpu,features} attributes to avoid miscompilations
such as using the wrong relocation type to access globals (missing
tagged-globals feature), clobbering registers specified via -ffixed-*
(missing reserve-* feature), and so on.
There's already a number of attributes copied from the module flags
onto functions created by createWithDefaultAttr(). I don't think
module flags are the right choice for the target attributes because
we don't need the conflict resolution logic between modules with
different target attributes, nor does it seem sensible to add it:
there's no unambiguously "correct" set of target attributes when
merging two modules with different attributes, and nor should there
be; it's perfectly valid for two modules to be compiled with different
target attributes, that's the whole reason why they are per-function.
This also implies that it's unnecessary to serialize the attributes in
bitcode, which implies that they shouldn't be stored on the module. We
can also observe that for the most part, createWithDefaultAttr()
is called from compiler passes such as sanitizers, coverage and
profiling passes that are part of the compile time pipeline, not
the LTO pipeline. This hints at a solution: we need to store the
attributes in a non-serialized location associated with the ambient
compilation context. Therefore in this patch I elected to store the
attributes on the LLVMContext.
There are calls to createWithDefaultAttr() in the NVPTX and AMDGPU
backends, and those calls would happen at LTO time. For those callers,
the bug still potentially exists and it would be necessary to refactor
them to create the functions at compile time if this issue is relevant
on those platforms.
Fixes #93633.
Reviewers: fmayer, MaskRay, eugenis
Reviewed By: MaskRay
Pull Request: https://github.com/llvm/llvm-project/pull/96721
Commit: 35f7b60aa6105753859bcccaf4a793aaf16b4acd
https://github.com/llvm/llvm-project/commit/35f7b60aa6105753859bcccaf4a793aaf16b4acd
Author: Vikram Hegde <115221833+vikramRH at users.noreply.github.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx10.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx11.cl
M llvm/docs/AMDGPUUsage.rst
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/intrinsics.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ptr.ll
M llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
M llvm/test/Verifier/AMDGPU/intrinsic-immarg.ll
Log Message:
-----------
[AMDGPU] Extend permlane16, permlanex16 and permlane64 intrinsic lowering for generic types (#92725)
These are incremental changes over #89217 , with core logic being the
same. This patch along with #89217 and #91190 should get us ready to enable 64
bit optimizations in atomic optimizer.
Commit: cb3469a30f875b9cd54a263803fffc93554bec12
https://github.com/llvm/llvm-project/commit/cb3469a30f875b9cd54a263803fffc93554bec12
Author: Jacob Lalonde <jalalonde at fb.com>
Date: 2024-06-25 (Tue, 25 Jun 2024)
Changed paths:
M lldb/source/Plugins/ObjectFile/Minidump/ObjectFileMinidump.cpp
Log Message:
-----------
Removed header and validated on new windows machine (#96724)
In #95312 uint and `#include <unistd.h>` were introduced. These broke
the windows build. I addressed uint in #96564, but include went unfixed.
So I acquired myself a windows machine to validate.
Commit: 2ee2b6aa7a3d9ba6ba13f6881b25e26d7d12c823
https://github.com/llvm/llvm-project/commit/2ee2b6aa7a3d9ba6ba13f6881b25e26d7d12c823
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M clang/lib/Sema/ScopeInfo.cpp
M clang/test/SemaCXX/coroutine-vla.cpp
Log Message:
-----------
[Coroutines] Clear FirstVLALoc in time
Unlike other *Loc member in FunctionScopeInfo, we didn't clear
FirstVLALoc in 'FunctionScopeInfo::Clear()'. Then it will be
problematic for the following case:
```
void bar(int n) {
int array[n];
return;
}
coroutine foo(int n) {
co_return;
}
```
When we parse `foo`, the FirstVLALoc is still valid, then the compiler
will report `vla in coroutine` error in bar, which is super odd. After
this patch, we can fix this.
Commit: c01ce797619359ee282773dfc4b1e91ff0a30435
https://github.com/llvm/llvm-project/commit/c01ce797619359ee282773dfc4b1e91ff0a30435
Author: Matthias Springer <me at m-sp.org>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M mlir/lib/Transforms/Utils/DialectConversion.cpp
Log Message:
-----------
[mlir][Transforms][NFC] Dialect Conversion: Move argument materialization logic (#96329)
This commit moves the argument materialization logic from
`legalizeConvertedArgumentTypes` to
`legalizeUnresolvedMaterializations`.
Before this change:
- Argument materializations were created in
`legalizeConvertedArgumentTypes` (which used to call
`materializeLiveConversions`).
After this change:
- `legalizeConvertedArgumentTypes` creates a "placeholder"
`unrealized_conversion_cast`.
- The placeholder `unrealized_conversion_cast` is replaced with an
argument materialization (using the type converter) in
`legalizeUnresolvedMaterializations`.
- All argument and target materializations now take place in the same
location (`legalizeUnresolvedMaterializations`).
This commit brings us closer towards creating all source/target/argument
materializations in one central step, which can then be made optional
(and delegated to the user) in the future. (There is one more source
materialization step that has not been moved yet.)
This commit also consolidates all `build*UnresolvedMaterialization`
functions into a single `buildUnresolvedMaterialization` function.
Commit: a159b36724d9b7dc67702d742ffd63503f6a1417
https://github.com/llvm/llvm-project/commit/a159b36724d9b7dc67702d742ffd63503f6a1417
Author: McCowan Zhang <86526121+mccowanzhang at users.noreply.github.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M mlir/include/mlir/Dialect/ControlFlow/IR/ControlFlowOps.td
M mlir/lib/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation.cpp
M mlir/lib/Dialect/ControlFlow/IR/ControlFlowOps.cpp
A mlir/test/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation/misc-other.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-bufferize.mlir
Log Message:
-----------
Bufferization with ControlFlow Asserts (#95868)
Fixed incorrect bufferization interaction with cf.assert
- reordered bufferization condition checking
- fixed hasNeitherAllocateNorFreeSideEffect checking bug
- implemented memory interface for cf.assert
---------
Co-authored-by: McCowan Zhang <mccowan.z at ssi.samsung.com>
Commit: 1822e3183d92e1bb9a742038e1dac3fb70b39028
https://github.com/llvm/llvm-project/commit/1822e3183d92e1bb9a742038e1dac3fb70b39028
Author: Heejin Ahn <aheejin at gmail.com>
Date: 2024-06-25 (Tue, 25 Jun 2024)
Changed paths:
A llvm/test/CodeGen/WebAssembly/target-features-attrs.ll
R llvm/test/CodeGen/WebAssembly/target-features.ll
Log Message:
-----------
[WebAssembly] Rename target-features.ll (#96716)
I'm planning on a PR that splits `target-features.ll` into two different
files and fix some other stuff on them:
- `target-features-attrs.ll` that tests target features by bitcode
function attributes and `-mattr=` options
- `target-features-cpus.ll` that tests target features by `-mcpu=`
options
But `target-features-attrs.ll` will share a bulk of the lines with the
current `target-features.ll`. And if I remove `target-features.ll` and
create the two new files in a single PR, git doesn't recognize either of
them as a copy (I hoped at least `target-features-attrs.ll` would be
recognized as a copy because it shares many lines with the current file)
So to make the diff smaller and easier to review, I'm renaming the file
first. I'll follow up with the PR that does the actual splitting.
Commit: 8426586f8709c771054ef5f84410fb9fcd83dbee
https://github.com/llvm/llvm-project/commit/8426586f8709c771054ef5f84410fb9fcd83dbee
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M compiler-rt/lib/profile/InstrProfilingFile.c
Log Message:
-----------
Revert "Reformat", due to wrong version of clang-format.
This reverts commit f4ce3448be9c47c61755197173a6a9e9b612dff8.
Commit: 20683de70e43fa73536ac1e8ce4082604048d040
https://github.com/llvm/llvm-project/commit/20683de70e43fa73536ac1e8ce4082604048d040
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/apx/adc.ll
M llvm/test/CodeGen/X86/apx/add.ll
M llvm/test/CodeGen/X86/apx/and.ll
M llvm/test/CodeGen/X86/apx/ctest.ll
M llvm/test/CodeGen/X86/apx/dec.ll
M llvm/test/CodeGen/X86/apx/inc.ll
M llvm/test/CodeGen/X86/apx/neg.ll
M llvm/test/CodeGen/X86/apx/not.ll
M llvm/test/CodeGen/X86/apx/or.ll
M llvm/test/CodeGen/X86/apx/sar.ll
M llvm/test/CodeGen/X86/apx/sbb.ll
M llvm/test/CodeGen/X86/apx/shl.ll
M llvm/test/CodeGen/X86/apx/shr.ll
M llvm/test/CodeGen/X86/apx/sub.ll
M llvm/test/CodeGen/X86/apx/xor.ll
M llvm/test/CodeGen/X86/popcnt.ll
Log Message:
-----------
[X86][CodeGen] Not promote some binary ops from i16 to i32 if we have NDD variant
Commit: eaae63d8e1430179f94c3bf8e2025067c3ff5975
https://github.com/llvm/llvm-project/commit/eaae63d8e1430179f94c3bf8e2025067c3ff5975
Author: Hui <hui.xie1990 at gmail.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M libcxx/docs/Status/Cxx20Issues.csv
M libcxx/include/__memory/shared_ptr.h
M libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.const/nullptr_t_deleter.pass.cpp
M libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.const/nullptr_t_deleter_allocator.pass.cpp
M libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.const/pointer.pass.cpp
M libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.const/pointer_deleter.pass.cpp
M libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.const/pointer_deleter_allocator.pass.cpp
A libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.const/types.h
Log Message:
-----------
"[libc++] Try again LWG3233 Broken requirements for shared_ptr converting constructors" (#96103)
Try it again. Use the approach suggested by Tim in the LWG thread :
using function default argument SFINAE
- Revert "[libc++] Revert LWG3233 Broken requirements for shared_ptr
converting constructors (#93071)"
- Revert "[libc++] Revert temporary attempt to implement LWG 4110
(#95263)"
- test for default_delete
- Revert "Revert "[libc++] Revert temporary attempt to implement LWG
4110 (#95263)""
- test for NULL
Commit: 569faa4dc04cf6849057e56ef07b56ad27f6ef9e
https://github.com/llvm/llvm-project/commit/569faa4dc04cf6849057e56ef07b56ad27f6ef9e
Author: Richard Smith <richard at metafoo.co.uk>
Date: 2024-06-25 (Tue, 25 Jun 2024)
Changed paths:
M clang/docs/LanguageExtensions.rst
Log Message:
-----------
Add documentation for `__builtin_object_size`. (#96573)
Explicitly describe how the Clang builtin works, given that it's not
exactly the same as GCC's builtin of the same name -- but is drop-in
compatible.
Fixes #95635.
Commit: 28a3fbbe8c6cd5b92fb0a2a3cc21a836a381e086
https://github.com/llvm/llvm-project/commit/28a3fbbe8c6cd5b92fb0a2a3cc21a836a381e086
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/test/CodeGen/X86/apx/compress-evex.mir
Log Message:
-----------
[X86][test] Pre-commit test for disabling NDD2NonNDD transform for 8/16-bit ops
Commit: 6c4c44b50ba3a08106b37fd5a739c387fef0b961
https://github.com/llvm/llvm-project/commit/6c4c44b50ba3a08106b37fd5a739c387fef0b961
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/include/llvm/ADT/SetOperations.h
M llvm/unittests/ADT/SetOperationsTest.cpp
Log Message:
-----------
[SetOperations] Support set containers with remove_if (#96613)
The current set_intersect implementation only works for std::set style
sets that have a value-erase method that does not invalidate iterators.
As such, it cannot be used for set containers like SetVector, which only
has iterator-invalidating erase.
Support such set containers by calling the remove_if method instead, if
it exists. The detection code is adopted from how contains() is detected
inside llvm::is_contained().
Commit: 515e048e36d9036506b0a9ea34aa20c2f65c25a7
https://github.com/llvm/llvm-project/commit/515e048e36d9036506b0a9ea34aa20c2f65c25a7
Author: AtariDreams <gfunni234 at gmail.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
Log Message:
-----------
[InstCombine] Simplify commutative matchers (NFC) (#96665)
Commit: dbd0c031366a1373db6dbe42186351568f526e56
https://github.com/llvm/llvm-project/commit/dbd0c031366a1373db6dbe42186351568f526e56
Author: Alexis Engelke <engelke at in.tum.de>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/lib/MC/MCDwarf.cpp
Log Message:
-----------
[MC][DWARF][NFC] Drop CIEKey map (#96075)
We already sort frames by their CIEKey, so we know that we only need to
update the CIE symbol when the CIE key changes. No need for a DenseMap.
Commit: 54cb5ca9f48fc542b920662a0eee7c0e6f35bee0
https://github.com/llvm/llvm-project/commit/54cb5ca9f48fc542b920662a0eee7c0e6f35bee0
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M libcxx/include/__utility/pair.h
Log Message:
-----------
[libc++][NFC] Simplify pair a bit (#96165)
Commit: be00190ce35807c8586ee4e2e61507fc0221e825
https://github.com/llvm/llvm-project/commit/be00190ce35807c8586ee4e2e61507fc0221e825
Author: Haohai Wen <haohai.wen at intel.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/lib/Target/X86/X86InstrInfo.cpp
Log Message:
-----------
[TII][X86] Do not schedule frame-setup/frame-destory instructions (#96611)
frame-setup/frame-destroy instruction can not be scheduled around by
PostRAScheduler. Their order is critical for SEH.
Commit: 1dbc2aad68f29f9d6306f6329610e1eca8afb3fe
https://github.com/llvm/llvm-project/commit/1dbc2aad68f29f9d6306f6329610e1eca8afb3fe
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/lib/Passes/PassBuilder.cpp
M llvm/test/tools/llc/new-pm/pipeline.mir
Log Message:
-----------
[PassBuilder] Parse machine function analyses inside require/invalidate (#96634)
Now we have several machine function analyses but forgot to support them
in `parseMachinePass`.
Commit: 8681bb8bedf065abe34a4523fb58287fc05f7907
https://github.com/llvm/llvm-project/commit/8681bb8bedf065abe34a4523fb58287fc05f7907
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
A llvm/test/Transforms/LoopVectorize/RISCV/vf-will-not-generate-any-vector-insts.ll
A llvm/test/Transforms/LoopVectorize/WebAssembly/induction-branch-cost.ll
A llvm/test/Transforms/LoopVectorize/WebAssembly/lit.local.cfg
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/optsize.ll
Log Message:
-----------
[LV] Add additional test coverage for cost modeling.
Add missing tests uncovered by
https://github.com/llvm/llvm-project/pull/92555.
Includes test for https://github.com/llvm/llvm-project/issues/96294 and
https://github.com/llvm/llvm-project/issues/96328
Commit: 5b4000dc58572d08754f0b2199c2046871ec8507
https://github.com/llvm/llvm-project/commit/5b4000dc58572d08754f0b2199c2046871ec8507
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/include/llvm/Analysis/VectorUtils.h
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
Log Message:
-----------
[VectorUtils] Add llvm::scaleShuffleMaskElts wrapper for narrowShuffleMaskElts/widenShuffleMaskElts, NFC. (#96646)
Using the target number of vector elements, scaleShuffleMaskElts will try to use narrowShuffleMaskElts/widenShuffleMaskElts to scale the shuffle mask accordingly.
Working on #58895 I didn't want to create yet another case where we have to handle both re-scaling cases.
Commit: 90e4eb8a479dbef4f98f7d8ccd2de5494c6366c7
https://github.com/llvm/llvm-project/commit/90e4eb8a479dbef4f98f7d8ccd2de5494c6366c7
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M clang/lib/AST/Interp/Interp.cpp
Log Message:
-----------
[clang][Interp][NFC] Add more source ranges to diagnostics
Commit: f782ff8fc6426890863be0791a9ace2394da3887
https://github.com/llvm/llvm-project/commit/f782ff8fc6426890863be0791a9ace2394da3887
Author: Benji Smith <6193112+Benjins at users.noreply.github.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/docs/ReleaseNotes.rst
M llvm/include/llvm-c/Core.h
M llvm/lib/IR/Core.cpp
M llvm/test/Bindings/llvm-c/echo.ll
M llvm/tools/llvm-c-test/echo.cpp
Log Message:
-----------
[C API] Add getters for Target Extension Types to C API (#96447)
Accessors for the name, type parameters, and integer parameters are
added. A test is added to echo.ll
This was originally done in
https://github.com/llvm/llvm-project/pull/71291 but that has been stale
for several months. This re-applies the changes, but with some tweaks.
e.g. removing the bulk getters in favour of a simple get-by-index
approach for the type/integer parameters. The latter is more in line
with the rest of the API
Commit: 16f349251fabacfdba4acac3b25baf0e6890c1a0
https://github.com/llvm/llvm-project/commit/16f349251fabacfdba4acac3b25baf0e6890c1a0
Author: Hui <hui.xie1990 at gmail.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M libcxx/include/__expected/expected.h
M libcxx/test/std/utilities/expected/expected.expected/ctor/ctor.copy.pass.cpp
Log Message:
-----------
[libc++] restrict the expected conversion constructor not compete against copy constructor (#96101)
fixes #92676
So right now clang does not like
```
std::expected<std::any, int> e1;
auto e2 = e1;
```
So basically when clang tries to do overload resolution of `auto e2 =
e1;`
It finds
```
expected(const expected&); // 1. This is OK
expected(const expected<_Up, _OtherErr>&) requires __can_convert; // 2. This needs to check its constraints
```
Then in `__can_convert`, one of the check is
```
_Not<is_constructible<_Tp, expected<_Up, _OtherErr>&>>
```
which is checking
```
is_constructible<std::any, expected<_Up, _OtherErr>&>
```
Then it looks at `std::any`'s constructor
```
template < class _ValueType,
class _Tp = decay_t<_ValueType>,
class = enable_if_t< !is_same<_Tp, any>::value && !__is_inplace_type<_ValueType>::value &&
is_copy_constructible<_Tp>::value> >
any(_ValueType&& __value);
```
In the above, `is_copy_constructible<_Tp>` expands to
```
is_copy_constructible<std::expected<std::any, int>>
```
And the above goes back to the original thing we asked : copy the
`std::expected`, which goes to the overload resolution again.
```
expected(const expected&);
expected(const expected<_Up, _OtherErr>&) requires __can_convert;
```
So the second overload results in a logical cycle.
I am not a language lawyer. We could argue that clang should give up on
the second overload which has logical cycle, as the first overload is a
perfect match.
Anyway, the fix in this patch tries to short-circuiting the second
overload's constraint check: that is, if the argument matches exact same
`expected<T, E>`, we give up immediately and let the copy constructor to
deal with it
Commit: cca4f549bddd28742f370571296b46054c98d27b
https://github.com/llvm/llvm-project/commit/cca4f549bddd28742f370571296b46054c98d27b
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp
Log Message:
-----------
[InstCombine][X86] Avoid repeated getType() calls when folding blendv->select. NFC.
Cleanup prep work for #58895
Commit: c9fc960650223ffb89c93d21d0d4c59648ee1c13
https://github.com/llvm/llvm-project/commit/c9fc960650223ffb89c93d21d0d4c59648ee1c13
Author: CarolineConcatto <caroline.concatto at arm.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M clang/include/clang/Basic/arm_sme.td
A clang/test/CodeGen/aarch64-sme2p1-intrinsics/acle_sme2p1_movaz.c
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/SMEInstrFormats.td
A llvm/test/CodeGen/AArch64/sme2p1-intrinsics-movaz.ll
Log Message:
-----------
[CLANG][LLVM][AArch64]SME2.1 intrinsics for MOVAZ tile to 2/4 vectors (#88710)
According to the specification in
ARM-software/acle#309 this adds the intrinsics
// Variants are also available for _za8_u8, _za16_s16, _za16_u16, //
_za16_f16, _za16_bf16, _za32_s32, _za32_u32, _za32_f32, // _za64_s64,
_za64_u64 and _za64_f64
svint8x2_t svreadz_hor_za8_s8_vg2(uint64_t tile, uint32_t slice)
__arm_streaming __arm_inout("za");
// Variants are also available for _za8_u8, _za16_s16, _za16_u16, //
_za16_f16, _za16_bf16, _za32_s32, _za32_u32, _za32_f32, // _za64_s64,
_za64_u64 and _za64_f64
svint8x4_t svreadz_hor_za8_s8_vg4(uint64_t tile, uint32_t slice)
__arm_streaming __arm_inout("za");
// Variants are also available for _za8_u8, _za16_s16, _za16_u16, //
_za16_f16, _za16_bf16, _za32_s32, _za32_u32, _za32_f32, // _za64_s64,
_za64_u64 and _za64_f64
svint8x2_t svreadz_ver_za8_s8_vg2(uint64_t tile, uint32_t slice)
__arm_streaming __arm_inout("za");
// Variants are also available for _za8_u8, _za16_s16, _za16_u16, //
_za16_f16, _za16_bf16, _za32_s32, _za32_u32, _za32_f32, // _za64_s64,
_za64_u64 and _za64_f64
svint8x4_t svreadz_ver_za8_s8_vg4(uint64_t tile, uint32_t slice)
__arm_streaming __arm_inout("za");
Commit: 847d046a82a760caa1b05206d77ed0b3d7bd4be6
https://github.com/llvm/llvm-project/commit/847d046a82a760caa1b05206d77ed0b3d7bd4be6
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M clang/lib/AST/Interp/Pointer.h
M clang/test/AST/Interp/arrays.cpp
Log Message:
-----------
[clang][Interp] Fix comparing one-past-the-end pointers
Commit: d6f906eadbf7a5c2eb484f62740bf3e6a650bc92
https://github.com/llvm/llvm-project/commit/d6f906eadbf7a5c2eb484f62740bf3e6a650bc92
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/include/llvm/CodeGen/SlotIndexes.h
M llvm/lib/CodeGen/SlotIndexes.cpp
M llvm/unittests/CodeGen/MLRegAllocDevelopmentFeatures.cpp
Log Message:
-----------
[SlotIndexes] Use simple_ilist instead of ilist. NFC. (#96747)
simple_ilist does not take ownership of its nodes, which is fine for
SlotIndexes because the IndexListEntry nodes are allocated with a
BumpPtrAllocator and do not need to be freed.
Commit: 86860be2886283210083e5e3f20048e559cc059e
https://github.com/llvm/llvm-project/commit/86860be2886283210083e5e3f20048e559cc059e
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M libc/src/stdlib/CMakeLists.txt
M libc/src/stdlib/rand.cpp
M libc/src/stdlib/rand_util.cpp
M libc/src/stdlib/rand_util.h
M libc/src/stdlib/srand.cpp
M libc/test/src/stdlib/rand_test.cpp
Log Message:
-----------
[libc] Make 'rand()' thread-safe using atomics instead of TLS (#96692)
Summary:
Currently, we implement the `rand` function using thread-local storage.
This is somewhat problematic because not every target supports TLS, and
even more do not support non-zero initializers on TLS.
The C standard states that the `rand()` function need not be thread,
safe. However, many implementations provide thread-safety anyway.
There's some confusing language in the 'rationale' section of
https://pubs.opengroup.org/onlinepubs/9699919799/functions/rand.html,
but given that `glibc` uses a lock, I think we should make this thread
safe as well. it mentions that threaded behavior is desirable and can be
done in the two ways:
1. A single per-process sequence of pseudo-random numbers that is shared
by all threads that call rand()
2. A different sequence of pseudo-random numbers for each thread that
calls rand()
The current implementation is (2.) and this patch moves it to (1.). This
is beneficial for the GPU case and more generic support. The downside is
that it's slightly slower to do these atomic operations, the fast path
will be two atomic reads and an atomic write.
Commit: 317f782ef2366950e6cdc0de9d35df7fcc15ec5d
https://github.com/llvm/llvm-project/commit/317f782ef2366950e6cdc0de9d35df7fcc15ec5d
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/include/llvm/ADT/SmallPtrSet.h
M llvm/unittests/ADT/SmallPtrSetTest.cpp
Log Message:
-----------
[ADT] Return bool from SmallPtrSet::remove_if()
Return whether anything was removed. This matches the API of
SetVector::remove_if() and is convenient for some future uses.
Commit: 92715cf43b18d497cd034bdc7787b3a8eeb2edc5
https://github.com/llvm/llvm-project/commit/92715cf43b18d497cd034bdc7787b3a8eeb2edc5
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/test/CodeGen/X86/avg.ll
M llvm/test/CodeGen/X86/avgceils-scalar.ll
M llvm/test/CodeGen/X86/avgceilu-scalar.ll
M llvm/test/CodeGen/X86/avgfloors-scalar.ll
M llvm/test/CodeGen/X86/avgflooru-scalar.ll
Log Message:
-----------
[DAG] expandAVG - attempt to extend to a wider integer type for the add/shift to avoid overflow handling (#95788)
Commit: 6f582b7ed3dcd220a2154b617d6469c142805d7c
https://github.com/llvm/llvm-project/commit/6f582b7ed3dcd220a2154b617d6469c142805d7c
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP][NFC]Remove extra check for VU.
Commit: 4c9b71dd9171164efbb99de5e75d4fcadf0e21b5
https://github.com/llvm/llvm-project/commit/4c9b71dd9171164efbb99de5e75d4fcadf0e21b5
Author: Serge Pavlov <sepavloff at gmail.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
M llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
M llvm/test/CodeGen/ARM/GlobalISel/fpenv.ll
Log Message:
-----------
[GlobalISel][ARM] Legalze set_fpmode and get_fpmode (#96467)
Implement handling of get/set floating point control modes for ARM in
Global Instruction Selector.
Commit: b6a94b6bfb2cbcfcb64c354d3ab876ec52bfcd14
https://github.com/llvm/llvm-project/commit/b6a94b6bfb2cbcfcb64c354d3ab876ec52bfcd14
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
Log Message:
-----------
[OMPIRBuilder] Use SmallPtrSet::remove_if() (NFC)
Commit: 519dbc6b996d6121e95cc14865d7e0fa6496bb12
https://github.com/llvm/llvm-project/commit/519dbc6b996d6121e95cc14865d7e0fa6496bb12
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyExceptionInfo.cpp
Log Message:
-----------
[WasmExceptionInfo] Use SmallPtrSet::remove_if() (NFC)
Commit: 177cbd16663a2ca36d0d7145c3b62f2d756f8f7f
https://github.com/llvm/llvm-project/commit/177cbd16663a2ca36d0d7145c3b62f2d756f8f7f
Author: Caroline Concatto <caroline.concatto at arm.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M clang/test/CodeGen/aarch64-sme2p1-intrinsics/acle_sme2p1_movaz.c
Log Message:
-----------
[Clang][SME2.1] Add REQUIRES: aarch64-registered-target to test
PR#88710 is failing because the test file needs
REQUIRES: aarch64-registered-target
Commit: d42b392696fbd9d612ac22ff82b4a1760fc26d89
https://github.com/llvm/llvm-project/commit/d42b392696fbd9d612ac22ff82b4a1760fc26d89
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/include/llvm/Analysis/VectorUtils.h
M llvm/lib/Analysis/VectorUtils.cpp
Log Message:
-----------
[VectorUtils] Use SmallPtrSet::remove_if() (NFC)
Commit: 6f8efc76c9b9d1fc02f043cb908a8aa655290a61
https://github.com/llvm/llvm-project/commit/6f8efc76c9b9d1fc02f043cb908a8aa655290a61
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/test/Transforms/PhaseOrdering/X86/pr67803.ll
Log Message:
-----------
[PhaseOrdering][X86] Regenerate pr67803.ll
Commit: dfe80a73223edff5c53f8be7925d302883cb40bc
https://github.com/llvm/llvm-project/commit/dfe80a73223edff5c53f8be7925d302883cb40bc
Author: martinboehme <mboehme at google.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M clang/include/clang/Analysis/FlowSensitive/ASTOps.h
M clang/unittests/Analysis/FlowSensitive/TransferTest.cpp
Log Message:
-----------
[clang][dataflow] Teach `AnalysisASTVisitor` that `typeid()` can be evaluated. (#96731)
We were previously treating the operand of `typeid()` as being
definitely
unevaluated, but it can be evaluated if it is a glvalue of polymorphic
type.
This patch includes a test that fails without the fix.
Commit: 85f47fdd039549ed7e89b53ca34b0b35456ffe3d
https://github.com/llvm/llvm-project/commit/85f47fdd039549ed7e89b53ca34b0b35456ffe3d
Author: martinboehme <mboehme at google.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M clang/lib/Analysis/FlowSensitive/Transfer.cpp
M clang/unittests/Analysis/FlowSensitive/TransferTest.cpp
Log Message:
-----------
[clang][nullability] Improve modeling of `++`/`--` operators. (#96601)
We definitely know that these operations change the value of their
operand, so
clear out any value associated with it. We don't create a new value,
instead
leaving it to the analysis to do this if desired.
Commit: e24a21291ac35a0660ec7cf19d4c36019ee7437e
https://github.com/llvm/llvm-project/commit/e24a21291ac35a0660ec7cf19d4c36019ee7437e
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M clang/include/clang/Parse/Parser.h
M clang/lib/Parse/ParseOpenMP.cpp
Log Message:
-----------
[clang][OpenMP] Shorten directive classification in ParseOpenMP (#94691)
Use directive categories to simplify long lists of `case` statements in
the OpenMP parser. This is a step towards avoiding dependence on
explicitly specified sets of directives that can be expressed more
generically.
The upcoming OpenMP 6.0 will introduce many new combined directives, and
the more generically we handle directives, the easier the introduction
of the new standard will be.
---------
Co-authored-by: Alexey Bataev <a.bataev at outlook.com>
Commit: 352a836176b25abfdc26ddc5ddbd18288715a794
https://github.com/llvm/llvm-project/commit/352a836176b25abfdc26ddc5ddbd18288715a794
Author: David Green <david.green at arm.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
A llvm/test/Transforms/InstCombine/canonicalize-gep-mul.ll
M llvm/test/Transforms/InstCombine/getelementptr.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-gather-scatter.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-phi.ll
M llvm/test/Transforms/LoopVectorize/AArch64/uniform-args-call-variants.ll
M llvm/test/Transforms/LoopVectorize/SystemZ/addressing.ll
M llvm/test/Transforms/LoopVectorize/X86/interleaving.ll
M llvm/test/Transforms/LoopVectorize/induction.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/scalable-inductions.ll
M llvm/test/Transforms/LoopVectorize/scalable-loop-unpredicated-body-scalar-tail.ll
M llvm/test/Transforms/LowerMatrixIntrinsics/multiply-fused-loops.ll
Log Message:
-----------
[InstCombine] Canonicalize non-i8 gep of mul to i8 (#96606)
This is a small canonicalization for `gep i32, p, (mul x, C)` -> `gep
i8, p, (mul x, C*4)`, so that the mul can combine both of the constant
multiplications, and we take a small step towards canonicalizing more
geps to i8.
It currently doesn't attempt to check for multiple uses on the mul, but
that should be possible if it sounds better. Let me know what you think
of the idea in general.
Commit: b6240c371522c701be8a7a143aa166d277508cbe
https://github.com/llvm/llvm-project/commit/b6240c371522c701be8a7a143aa166d277508cbe
Author: Lucas Duarte Prates <lucas.prates at arm.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M clang/include/clang/Driver/Options.td
M clang/include/clang/Frontend/FrontendOptions.h
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/test/CodeGen/aarch64-targetattr.c
M clang/test/Driver/aarch64-fp16.c
M clang/test/Driver/aarch64-sve2.c
M clang/test/Driver/aarch64-v81a.c
M clang/test/Driver/aarch64-v82a.c
M clang/test/Driver/aarch64-v83a.c
M clang/test/Driver/aarch64-v84a.c
M clang/test/Driver/aarch64-v85a.c
M clang/test/Driver/aarch64-v86a.c
M clang/test/Driver/aarch64-v87a.c
M clang/test/Driver/aarch64-v88a.c
M clang/test/Driver/aarch64-v89a.c
A clang/test/Driver/aarch64-v8a.c
M clang/test/Driver/aarch64-v91a.c
M clang/test/Driver/aarch64-v92a.c
M clang/test/Driver/aarch64-v93a.c
M clang/test/Driver/aarch64-v94a.c
M clang/test/Driver/aarch64-v95a.c
A clang/test/Driver/aarch64-v9a.c
M clang/test/Driver/print-supported-extensions.c
M clang/test/Preprocessor/aarch64-target-features.c
M clang/tools/driver/cc1_main.cpp
M flang/test/Driver/target-cpu-features.f90
M llvm/include/llvm/MC/MCSubtargetInfo.h
M llvm/include/llvm/TargetParser/AArch64TargetParser.h
M llvm/lib/MC/MCSubtargetInfo.cpp
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/lib/TargetParser/AArch64TargetParser.cpp
M llvm/unittests/TargetParser/TargetParserTest.cpp
M llvm/utils/TableGen/ARMTargetDefEmitter.cpp
Log Message:
-----------
[AArch64] Add ability to list extensions enabled for a target (#95805)
This introduces the new `--print-enabled-extensions` command line option
to AArch64, which prints the list of extensions that are enabled for the
target specified by the combination of `--target`/`-march`/`-mcpu`
values.
The goal of the this option is both to enable the manual inspection of
the enabled extensions by users and to enhance the testability of
architecture versions and CPU targets implemented in the compiler.
As part of this change, a new field for `FEAT_*` architecture feature
names was added to the TableGen entries. The output of the existing
`--print-supported-extensions` option was updated accordingly to show
these in a separate column.
Commit: 00ae6bb6c27b5ca89fb22dff99a34d6b45e3e0b0
https://github.com/llvm/llvm-project/commit/00ae6bb6c27b5ca89fb22dff99a34d6b45e3e0b0
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/test/CodeGen/ARM/constant-islands-split-IT.mir
Log Message:
-----------
[ARM] Regenerate MIR test (NFC)
Commit: 6e96e5ab8a0e40fba0302a5c32574be41ef57354
https://github.com/llvm/llvm-project/commit/6e96e5ab8a0e40fba0302a5c32574be41ef57354
Author: martinboehme <mboehme at google.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M clang/include/clang/Analysis/FlowSensitive/ASTOps.h
M clang/unittests/Analysis/FlowSensitive/TransferTest.cpp
Log Message:
-----------
Revert "[clang][dataflow] Teach `AnalysisASTVisitor` that `typeid()` can be evaluated." (#96766)
Reverts llvm/llvm-project#96731
It causes CI failures.
Commit: e5e0d8739d4a2b70d7ad317863d7b168e4895b18
https://github.com/llvm/llvm-project/commit/e5e0d8739d4a2b70d7ad317863d7b168e4895b18
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/lib/AST/Interp/ByteCodeExprGen.h
M clang/test/SemaCXX/cxx0x-initializer-stdinitializerlist.cpp
Log Message:
-----------
[clang][Interp] Implement CXXStdInitializerListExprs
Commit: 161e1689ba98fabba71cac21f536708c78e9d7b0
https://github.com/llvm/llvm-project/commit/161e1689ba98fabba71cac21f536708c78e9d7b0
Author: Fred Grim <fgrim at apple.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M lld/test/ELF/as-needed-no-reloc.s
M lld/test/ELF/as-needed.s
M lld/test/ELF/auxiliary.s
M lld/test/ELF/dynamic-reloc.s
M lld/test/ELF/filter.s
M lld/test/ELF/gc-sections-shared.s
M lld/test/ELF/no-soname.s
M lld/test/ELF/partition-synthetic-sections.s
M lld/test/ELF/push-state.s
M lld/test/ELF/shared-ppc64.s
M lld/test/ELF/shared.s
M lld/test/ELF/soname.s
M lld/test/ELF/soname2.s
M lld/test/ELF/wrap-drop-shared-original.s
M llvm/test/tools/llvm-ifs/write-stub.test
M llvm/test/tools/llvm-readobj/ELF/dynamic-malformed.test
M llvm/test/tools/llvm-readobj/ELF/dynamic-tags.test
M llvm/test/tools/llvm-readobj/ELF/loadname.test
M llvm/tools/llvm-readobj/ELFDumper.cpp
Log Message:
-----------
[llvm-readobj][ELF] Test multivalued rpath entries and alter the output for readobj to emphasize the single valued nature of NEEDED, SONAME, USED etc. (#96562)
In the context of #95976 it became clear that the output for readobj
implied multi valued entries in several cases in the elf headers that
the documentation only allowed for a single value. DT_NEEDED is the
example here where the value is an offset into the string table without
any sort of separator that could give you multiple entries. This patch
alters the LLVM output so that the single valued nature is emphasized.
For example the output was:
```
DynamicSection [ (35 entries)
Tag Type Name/Value
0x000000000000001D RUNPATH Library runpath: [$ORIGIN/../lib:]
0x0000000000000001 NEEDED Shared library: [libm.so.6]
0x0000000000000001 NEEDED Shared library: [libz.so.1]
0x0000000000000001 NEEDED Shared library: [libzstd.so.1]
```
and is now
```
Tag Type Name/Value
0x000000000000001D RUNPATH Library runpath: [$ORIGIN/../lib:]
0x0000000000000001 NEEDED Shared library: libm.so.6
0x0000000000000001 NEEDED Shared library: libz.so.1
0x0000000000000001 NEEDED Shared library: libzstd.so.1
```
This pr also tests that multi-valued rpaths are handled correctly in the
JSON case (i.e. they become proper lists) like:
```
{
"Tag": 15,
"Type": "RPATH",
"Value": 9,
"Path": [
"x",
"w",
"U"
]
},
```
when separated by :
Commit: b579aacc30bc02e8430c0b59af644f52ece71160
https://github.com/llvm/llvm-project/commit/b579aacc30bc02e8430c0b59af644f52ece71160
Author: Lucas Duarte Prates <lucas.prates at arm.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M clang/include/clang/Driver/Options.td
M clang/include/clang/Frontend/FrontendOptions.h
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/test/CodeGen/aarch64-targetattr.c
M clang/test/Driver/aarch64-fp16.c
M clang/test/Driver/aarch64-sve2.c
M clang/test/Driver/aarch64-v81a.c
M clang/test/Driver/aarch64-v82a.c
M clang/test/Driver/aarch64-v83a.c
M clang/test/Driver/aarch64-v84a.c
M clang/test/Driver/aarch64-v85a.c
M clang/test/Driver/aarch64-v86a.c
M clang/test/Driver/aarch64-v87a.c
M clang/test/Driver/aarch64-v88a.c
M clang/test/Driver/aarch64-v89a.c
R clang/test/Driver/aarch64-v8a.c
M clang/test/Driver/aarch64-v91a.c
M clang/test/Driver/aarch64-v92a.c
M clang/test/Driver/aarch64-v93a.c
M clang/test/Driver/aarch64-v94a.c
M clang/test/Driver/aarch64-v95a.c
R clang/test/Driver/aarch64-v9a.c
M clang/test/Driver/print-supported-extensions.c
M clang/test/Preprocessor/aarch64-target-features.c
M clang/tools/driver/cc1_main.cpp
M flang/test/Driver/target-cpu-features.f90
M llvm/include/llvm/MC/MCSubtargetInfo.h
M llvm/include/llvm/TargetParser/AArch64TargetParser.h
M llvm/lib/MC/MCSubtargetInfo.cpp
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/lib/TargetParser/AArch64TargetParser.cpp
M llvm/unittests/TargetParser/TargetParserTest.cpp
M llvm/utils/TableGen/ARMTargetDefEmitter.cpp
Log Message:
-----------
Revert "[AArch64] Add ability to list extensions enabled for a target" (#96768)
Reverts llvm/llvm-project#95805 due to test failures caught by the
buildbots.
Commit: dead8f845f2549db5dec16b59b80d3e321948674
https://github.com/llvm/llvm-project/commit/dead8f845f2549db5dec16b59b80d3e321948674
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M clang/lib/AST/Interp/Pointer.h
M clang/test/AST/Interp/arrays.cpp
Log Message:
-----------
[clang][Interp] Pointers into unknown-size arrays are never one-past-end
Commit: 019f525716348578802b02961c328b43f7cad0fb
https://github.com/llvm/llvm-project/commit/019f525716348578802b02961c328b43f7cad0fb
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M clang-tools-extra/clang-tidy/misc/UseInternalLinkageCheck.cpp
M clang-tools-extra/clang-tidy/misc/UseInternalLinkageCheck.h
M clang-tools-extra/docs/clang-tidy/checks/misc/use-internal-linkage.rst
A clang-tools-extra/test/clang-tidy/checkers/misc/use-internal-linkage-fix-mode-none.cpp
M clang-tools-extra/test/clang-tidy/checkers/misc/use-internal-linkage-func.cpp
M clang-tools-extra/test/clang-tidy/checkers/misc/use-internal-linkage-var.cpp
Log Message:
-----------
[clang-tidy] add fixhint for misc-use-internal-linkage (#96203)
Commit: fd35a92300a00edaf56ae94176317390677569a4
https://github.com/llvm/llvm-project/commit/fd35a92300a00edaf56ae94176317390677569a4
Author: Eisuke Kawashima <e.kawaschima+github at gmail.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M lldb/examples/python/crashlog.py
M lldb/examples/python/disasm-stress-test.py
M lldb/examples/summaries/cocoa/CFString.py
M lldb/examples/summaries/pysummary.py
M lldb/examples/synthetic/bitfield/example.py
M lldb/packages/Python/lldbsuite/test/lldbtest.py
M lldb/test/API/commands/command/script/welcome.py
M lldb/test/API/commands/expression/call-throws/TestCallThatThrows.py
M lldb/test/API/functionalities/disassemble/aarch64-adrp-add/TestAArch64AdrpAdd.py
M lldb/test/API/functionalities/gdb_remote_client/TestNoWatchpointSupportInfo.py
M lldb/test/API/tools/lldb-server/TestAppleSimulatorOSType.py
M lldb/test/API/tools/lldb-server/TestLldbGdbServer.py
Log Message:
-----------
[lldb] fix(lldb/**.py): fix comparison to True/False (#94039)
from PEP8
(https://peps.python.org/pep-0008/#programming-recommendations):
> Comparisons to singletons like None should always be done with is or
is not, never the equality operators.
Co-authored-by: Eisuke Kawashima <e-kwsm at users.noreply.github.com>
Commit: 586114510c5fa71d1377c7f53e68a3b12c472aa2
https://github.com/llvm/llvm-project/commit/586114510c5fa71d1377c7f53e68a3b12c472aa2
Author: Eisuke Kawashima <e.kawaschima+github at gmail.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M lldb/bindings/interface/SBBreakpointDocstrings.i
M lldb/bindings/interface/SBDataExtensions.i
M lldb/docs/use/python.rst
M lldb/examples/python/armv7_cortex_m_target_defintion.py
M lldb/packages/Python/lldbsuite/test/dotest.py
M lldb/packages/Python/lldbsuite/test/lldbtest.py
M lldb/packages/Python/lldbsuite/test/lldbutil.py
M lldb/packages/Python/lldbsuite/test/tools/intelpt/intelpt_testcase.py
M lldb/test/API/functionalities/breakpoint/address_breakpoints/TestBadAddressBreakpoints.py
M lldb/test/API/functionalities/step_scripted/TestStepScripted.py
M lldb/test/API/functionalities/stop-on-sharedlibrary-load/TestStopOnSharedlibraryEvents.py
M lldb/test/API/lua_api/TestLuaAPI.py
M lldb/test/API/macosx/thread_suspend/TestInternalThreadSuspension.py
M lldb/test/API/python_api/event/TestEvents.py
M lldb/test/API/python_api/process/read-mem-cstring/TestReadMemCString.py
M lldb/test/API/python_api/type/TestTypeList.py
M lldb/test/API/python_api/was_interrupted/interruptible.py
M lldb/test/Shell/lit.cfg.py
Log Message:
-----------
[lldb] fix(lldb/**.py): fix comparison to None (#94017)
from PEP8
(https://peps.python.org/pep-0008/#programming-recommendations):
> Comparisons to singletons like None should always be done with is or
is not, never the equality operators.
Co-authored-by: Eisuke Kawashima <e-kwsm at users.noreply.github.com>
Commit: 3e1ebd77e4e9a772e4f06f12d19c64860fb1f070
https://github.com/llvm/llvm-project/commit/3e1ebd77e4e9a772e4f06f12d19c64860fb1f070
Author: darkbuck <michael.hliao at gmail.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
Log Message:
-----------
[GlobalISel] Add support for lowering byref attribute
Reviewers: nikic, spaits, arsenm
Reviewed By: arsenm
Pull Request: https://github.com/llvm/llvm-project/pull/96733
Commit: 30b93db5476e3ae2efdaba25fb53fcc3c081da77
https://github.com/llvm/llvm-project/commit/30b93db5476e3ae2efdaba25fb53fcc3c081da77
Author: Matthew Weingarten <matt at weingarten.org>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M compiler-rt/include/profile/MIBEntryDef.inc
M compiler-rt/include/profile/MemProfData.inc
M compiler-rt/lib/memprof/memprof_allocator.cpp
M compiler-rt/lib/memprof/memprof_flags.inc
M compiler-rt/lib/memprof/memprof_mapping.h
M compiler-rt/lib/memprof/memprof_mibmap.cpp
M compiler-rt/lib/memprof/memprof_rawprofile.cpp
M compiler-rt/lib/memprof/memprof_rtl.cpp
M compiler-rt/lib/memprof/tests/rawprofile.cpp
M llvm/include/llvm/ProfileData/MIBEntryDef.inc
M llvm/include/llvm/ProfileData/MemProf.h
M llvm/include/llvm/ProfileData/MemProfData.inc
M llvm/include/llvm/ProfileData/MemProfReader.h
M llvm/lib/ProfileData/MemProfReader.cpp
M llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
M llvm/test/Transforms/PGOProfile/Inputs/memprof.exe
M llvm/test/Transforms/PGOProfile/Inputs/memprof.memprofraw
M llvm/test/Transforms/PGOProfile/Inputs/memprof.nocolinfo.exe
M llvm/test/Transforms/PGOProfile/Inputs/memprof.nocolinfo.memprofraw
M llvm/test/Transforms/PGOProfile/Inputs/memprof_internal_linkage.exe
M llvm/test/Transforms/PGOProfile/Inputs/memprof_internal_linkage.memprofraw
M llvm/test/Transforms/PGOProfile/Inputs/memprof_loop_unroll.exe
M llvm/test/Transforms/PGOProfile/Inputs/memprof_loop_unroll.memprofraw
M llvm/test/Transforms/PGOProfile/Inputs/memprof_missing_leaf.exe
M llvm/test/Transforms/PGOProfile/Inputs/memprof_missing_leaf.memprofraw
M llvm/test/Transforms/PGOProfile/memprof_internal_linkage.ll
A llvm/test/tools/llvm-profdata/Inputs/basic-histogram.memprofexe
A llvm/test/tools/llvm-profdata/Inputs/basic-histogram.memprofraw
M llvm/test/tools/llvm-profdata/Inputs/basic.memprofexe
M llvm/test/tools/llvm-profdata/Inputs/basic.memprofraw
A llvm/test/tools/llvm-profdata/Inputs/basic_v3.memprofexe
A llvm/test/tools/llvm-profdata/Inputs/basic_v3.memprofraw
M llvm/test/tools/llvm-profdata/Inputs/buildid.memprofexe
M llvm/test/tools/llvm-profdata/Inputs/buildid.memprofraw
M llvm/test/tools/llvm-profdata/Inputs/inline.memprofexe
M llvm/test/tools/llvm-profdata/Inputs/inline.memprofraw
M llvm/test/tools/llvm-profdata/Inputs/multi.memprofexe
M llvm/test/tools/llvm-profdata/Inputs/multi.memprofraw
A llvm/test/tools/llvm-profdata/Inputs/padding-histogram.memprofexe
A llvm/test/tools/llvm-profdata/Inputs/padding-histogram.memprofraw
M llvm/test/tools/llvm-profdata/Inputs/pic.memprofexe
M llvm/test/tools/llvm-profdata/Inputs/pic.memprofraw
M llvm/test/tools/llvm-profdata/Inputs/update_memprof_inputs.sh
A llvm/test/tools/llvm-profdata/memprof-basic-histogram.test
M llvm/test/tools/llvm-profdata/memprof-basic.test
A llvm/test/tools/llvm-profdata/memprof-basic_v3.test
M llvm/test/tools/llvm-profdata/memprof-inline.test
M llvm/test/tools/llvm-profdata/memprof-multi.test
A llvm/test/tools/llvm-profdata/memprof-padding-histogram.test
M llvm/test/tools/llvm-profdata/memprof-pic.test
M llvm/unittests/ProfileData/MemProfTest.cpp
Log Message:
-----------
[Memprof] Adds the option to collect AccessCountHistograms for memprof. (#94264)
Adds compile time flag -mllvm -memprof-histogram and runtime flag
histogram=true|false to turn Histogram collection on and off. The
-memprof-histogram flag relies on -memprof-use-callbacks=true to work.
Updates shadow mapping logic in histogram mode from having one 8 byte
counter for 64 bytes, to 1 byte for 8 bytes, capped at 255. Only
supports this granularity as of now.
Updates the RawMemprofReader and serializing MemoryInfoBlocks to binary
format, including changing to a new version of the raw binary format
from version 3 to version 4.
Updates creating MemoryInfoBlocks with and without Histograms. When two
MemoryInfoBlocks are merged, AccessCounts are summed up and the shorter
Histogram is removed.
Adds a memprof_histogram test case.
Initial commit for adding AccessCountHistograms up until RawProfile for
memprof
Commit: 17eaa23f7ecdfe79ad74552aaa260e6ce32432c2
https://github.com/llvm/llvm-project/commit/17eaa23f7ecdfe79ad74552aaa260e6ce32432c2
Author: Janek van Oirschot <janek.vanoirschot at amd.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h
M llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp
M llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.h
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h
M llvm/lib/Target/AMDGPU/SIProgramInfo.cpp
M llvm/lib/Target/AMDGPU/SIProgramInfo.h
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.ll
M llvm/test/MC/AMDGPU/hsa-sym-expr-failure.s
M llvm/test/MC/AMDGPU/hsa-sym-exprs-gfx10.s
M llvm/test/MC/AMDGPU/hsa-sym-exprs-gfx11.s
M llvm/test/MC/AMDGPU/hsa-sym-exprs-gfx12.s
M llvm/test/MC/AMDGPU/hsa-sym-exprs-gfx7.s
M llvm/test/MC/AMDGPU/hsa-sym-exprs-gfx8.s
M llvm/test/MC/AMDGPU/hsa-sym-exprs-gfx90a.s
M llvm/test/MC/AMDGPU/hsa-tg-split.s
M llvm/test/MC/AMDGPU/hsa-v4.s
M llvm/test/MC/AMDGPU/hsa-v5-uses-dynamic-stack.s
M llvm/unittests/MC/AMDGPU/CMakeLists.txt
R llvm/unittests/MC/AMDGPU/SIProgramInfoMCExprs.cpp
Log Message:
-----------
[AMDGPU] MCExpr-ify AMDGPU HSAMetadata (#94788)
Enables MCExpr for HSAMetadata, particularly, HSAMetadata's msgpack format.
Commit: b7762f2e64af34506447b56eea7bdbabd8568718
https://github.com/llvm/llvm-project/commit/b7762f2e64af34506447b56eea7bdbabd8568718
Author: Balazs Benics <benicsbalazs at gmail.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/CMakeLists.txt
Log Message:
-----------
Bump required minimal Z3 version from 4.7.1 to 4.8.9 (#96682)
https://discourse.llvm.org/t/bump-minimal-z3-requirements-from-4-7-1-to-4-8-9/79664
This supposed to unblock #95128 and #95129.
Commit: 2612765faf0e72cc57c6cce058305ddf241c3e3c
https://github.com/llvm/llvm-project/commit/2612765faf0e72cc57c6cce058305ddf241c3e3c
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/test/CodeGen/NVPTX/combine-mad.ll
Log Message:
-----------
[NVPTX] Fold (add (select 0, (mul a, b)), c) -> (select c, (mad a, b, c)) (#96352)
Add folding for `(add (select cond, 0, (mul a, b)), c)` to `(select
cond, c, (mad a, b, c))`. Also, refactor the DAG folding implementation
to separate out the `ADD` and `FADD` folding cases.
Commit: 19183691f32c8cc6967322523f6fa338617929bd
https://github.com/llvm/llvm-project/commit/19183691f32c8cc6967322523f6fa338617929bd
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/is-fpclass-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/is-fpclass-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-is-fpclass-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-is-fpclass-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-rv64.mir
Log Message:
-----------
[RISCV][GISel] Add missing fclass tests. NFC (#96694)
We were only testing f32 on rv32 and f64 on rv64. We need to test f32
and f64 on both rv32 and rv64.
Commit: d0527ab69765740c1747695bbfe72a3db1781b16
https://github.com/llvm/llvm-project/commit/d0527ab69765740c1747695bbfe72a3db1781b16
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M libc/src/stdlib/rand.cpp
M libc/src/stdlib/srand.cpp
Log Message:
-----------
[libc] Fix Fuscia builder failing on atomic warnings (#96791)
Summary:
This function uses atomics now, which emit warnings on some platforms
that don't support full lock-free atomics. These aren't specifically
wrong, and in the future we could investigate a libc configuration
specialized for single-threaded microprocessors, but for now we should
get the bot running again.
Commit: 637b7f805a2f22978fac75e75c52bd6d7c3e8161
https://github.com/llvm/llvm-project/commit/637b7f805a2f22978fac75e75c52bd6d7c3e8161
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M libcxx/include/__ranges/iota_view.h
A libcxx/test/std/ranges/range.factories/range.iota.view/assert.ctor.value.bound.pass.cpp
Log Message:
-----------
[libc++] Classify iota_view precondition (#96662)
Fixes #91385
Commit: e1015ae55d9ac729b0b0a41f4207241f8d4b2789
https://github.com/llvm/llvm-project/commit/e1015ae55d9ac729b0b0a41f4207241f8d4b2789
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M libc/docs/gpu/support.rst
M libc/src/stdlib/rand_util.cpp
Log Message:
-----------
[libc][docs] List `rand` and `srand` as supported on the GPU (#96757)
Summary:
I initially didn't report these as supported because they didn't provide
expected behavior and were very wasteful. The recent patch moved them to
a lock-free atomic implementation so they can now actually be used.
Commit: acd6cb85b3c410e88dbcc9e48733d0e1ac70eadc
https://github.com/llvm/llvm-project/commit/acd6cb85b3c410e88dbcc9e48733d0e1ac70eadc
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fcmp-f16-rv32.mir
A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fcmp-f16-rv64.mir
A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/is-fpclass-f16-rv32.mir
A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/is-fpclass-f16-rv64.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fcmp-f16-rv32.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fcmp-f16-rv64.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-is-fpclass-f16-rv32.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-is-fpclass-f16-rv64.mir
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-f16-rv32.mir
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-f16-rv64.mir
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-f16-rv32.mir
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-f16-rv64.mir
Log Message:
-----------
[RISCV][GISel] Support fcmp and fclass for Zfh. (#96696)
Commit: 7c4fc9ccc058137877c99bad402a91d3ce640bbb
https://github.com/llvm/llvm-project/commit/7c4fc9ccc058137877c99bad402a91d3ce640bbb
Author: Xu Zhang <simonzgx at gmail.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M libc/src/__support/OSUtil/linux/fcntl.cpp
M libc/test/src/fcntl/CMakeLists.txt
M libc/test/src/fcntl/fcntl_test.cpp
Log Message:
-----------
[libc][fcntl] Simplify the handling of the return value from syscall … (#96325)
Fixes #95570
Commit: 581fd2fa573e39607ea164c0b4a8057baeb62c69
https://github.com/llvm/llvm-project/commit/581fd2fa573e39607ea164c0b4a8057baeb62c69
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-f16-rv32.mir
A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-f16-rv64.mir
A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-f16-rv32.mir
A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-f16-rv64.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-f16-rv32.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-f16-rv64.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-itofp-f16-rv32.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-itofp-f16-rv64.mir
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-f16-rv32.mir
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-f16-rv64.mir
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-f16-rv32.mir
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-f16-rv64.mir
Log Message:
-----------
[RISCV][GISel] Support fptoi and itofp for Zfh. (#96707)
Commit: 0d9172ecaca2b0834e65343aa24d7cfa4f6d841d
https://github.com/llvm/llvm-project/commit/0d9172ecaca2b0834e65343aa24d7cfa4f6d841d
Author: Vyacheslav Levytskyy <vyacheslav.levytskyy at intel.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/test/CodeGen/SPIRV/const-nested-vecs.ll
M llvm/test/CodeGen/SPIRV/pointers/global-zeroinitializer.ll
A llvm/test/CodeGen/SPIRV/pointers/irtrans-added-int-const-32-64.ll
Log Message:
-----------
[SPIR-V] Improve pattern matching and tracking of constant integers (#96615)
This PR fixes the issue
https://github.com/llvm/llvm-project/issues/96614 by improve pattern
matching and tracking of constant integers. The attached test is
successful if it doesn't crash and generate valid SPIR-V code for both
32 and 64 bits targets.
Commit: bb50bc23983052e70a6140d39fcc775362b03fc3
https://github.com/llvm/llvm-project/commit/bb50bc23983052e70a6140d39fcc775362b03fc3
Author: Vyacheslav Levytskyy <vyacheslav.levytskyy at intel.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/test/CodeGen/SPIRV/transcoding/OpGenericCastToPtr.ll
Log Message:
-----------
[SPIR-V] Fix support of OpGenericCastToPtr __spirv_ wrappers (#96655)
This PR completes implementation of insertion of OpGenericCastToPtr
using builtin functions started by
https://github.com/llvm/llvm-project/pull/95055 by:
* fixing errors in Tablegen definition,
* adding type inference info for `__spirv_GenericCastToPtrExplicit` kind
of wrappers, and
* hardening the test case to check correct translation of
`__spirv_GenericCastToPtrExplicit` kind of wrappers.
Commit: 378630b4d023e3de76a82ceb3b713f90cf308a7f
https://github.com/llvm/llvm-project/commit/378630b4d023e3de76a82ceb3b713f90cf308a7f
Author: Vyacheslav Levytskyy <vyacheslav.levytskyy at intel.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
M llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_add/atomicrmw_faddfsub_float.ll
Log Message:
-----------
[SPIR-V] Support cl_ext_float_atomics and fix errors in definition of atomic_fetch_*_explicit builtins (#96767)
This PR:
* supports cl_ext_float_atomics by mapping atomic_fetch_add and
atomic_fetch_sub applied to float arguments to the corresponding
instructions from SPV_EXT_shader_atomic_float*_add, and
* fix errors in definition of atomic_fetch_*_explicit builtins by fixing
a valid number of arguments.
Commit: 8ab66775dc885f7a99ee5f53771ce555e42085f9
https://github.com/llvm/llvm-project/commit/8ab66775dc885f7a99ee5f53771ce555e42085f9
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
Log Message:
-----------
[RISCV] Add Zfh to typeIsScalarFPArith and simplify code. NFC
Now that we have Zfh supported and tested for every opcode that uses
typeIsScalarFPArith, we can fold Zfh into it.
Commit: 868fae1f2ecb54604231c1334ce9aa5b4c0b1288
https://github.com/llvm/llvm-project/commit/868fae1f2ecb54604231c1334ce9aa5b4c0b1288
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-ext-trunc-f16.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-ext-trunc-f16.mir
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-ext-trunc-f16.mir
Log Message:
-----------
[RISCV][GISel] Support G_FPEXT/FPTRUNC with ZFh.
Commit: 141bea8c3cad62b381aef3c216cf7f78b812f580
https://github.com/llvm/llvm-project/commit/141bea8c3cad62b381aef3c216cf7f78b812f580
Author: Damyan Pepper <damyanp at microsoft.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/include/llvm/MC/DXContainerPSVInfo.h
M llvm/lib/Target/DirectX/DXContainerGlobals.cpp
A llvm/test/CodeGen/DirectX/ContainerData/PipelineStateValidation.ll
Log Message:
-----------
[DirectX] Add stub PSV0 section (#96712)
Direct3D requires a PSV0 section to be present in the DXContainer in
order to be able to load and use the shader.
This change adds a minimal stub PSV0, with some hard-coded values, that
are just enough to unblock loading into Direct3D.
Contributes to #90129
Commit: 0f24a462386409c1d907aefb9d8a58481cb71933
https://github.com/llvm/llvm-project/commit/0f24a462386409c1d907aefb9d8a58481cb71933
Author: Kyle Huey <khuey at kylehuey.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/lib/Support/CMakeLists.txt
Log Message:
-----------
[llvm-config] Make llvm-config --system-libs obey LLVM_USE_STATIC_ZSTD (#93754)
LLVM's build system does the right thing but LLVM_SYSTEM_LIBS ends up
containing the shared library. Emit the static library instead when
appropriate.
With LLVM_USE_STATIC_ZSTD, before:
khuey at zhadum:~/dev/llvm-project/build$ ./bin/llvm-config --system-libs
-lrt -ldl -lm -lz -lzstd -lxml2
after:
khuey at zhadum:~/dev/llvm-project/build$ ./bin/llvm-config --system-libs
-lrt -ldl -lm -lz /usr/local/lib/libzstd.a -lxml2
Commit: 3f78d89a2e6170d206a6b91a93b3fdf5e46ab6db
https://github.com/llvm/llvm-project/commit/3f78d89a2e6170d206a6b91a93b3fdf5e46ab6db
Author: Mingming Liu <mingmingl at google.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M compiler-rt/test/profile/Linux/instrprof-vtable-value-prof.cpp
M llvm/test/tools/llvm-profdata/vtable-value-prof.test
M llvm/tools/llvm-profdata/llvm-profdata.cpp
Log Message:
-----------
[TypeProf][InstrFDO]Omit vtable symbols in indexed profiles by default (#96520)
- The indexed iFDO profiles contains compressed vtable names for `llvm-profdata show --show-vtables` debugging
usage. An optimized build doesn't need it and doesn't decompress the blob now [1], since optimized binary has the
source code and IR to find vtable symbols.
- The motivation is to avoid increasing profile size when it's not necessary.
- This doesn't change the indexed profile format and thereby doesn't need a version change.
[1] https://github.com/llvm/llvm-project/blob/eac925fb81f26342811ad1765e8f9919628e2254/llvm/include/llvm/ProfileData/InstrProfReader.h#L696-L699
Commit: d29fdfbc4e3b42e9ee0295049493ba7b1471772f
https://github.com/llvm/llvm-project/commit/d29fdfbc4e3b42e9ee0295049493ba7b1471772f
Author: Joel E. Denny <jdenny.ornl at gmail.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/lib/LTO/LTOBackend.cpp
M llvm/test/Feature/load_plugin_error.ll
Log Message:
-----------
[LTO] Avoid assert fail on failed pass plugin load (#96691)
Without this patch, passing -load-pass-plugin=nonexistent.so to
llvm-lto2 produces a backtrace because LTOBackend.cpp does not handle
the error correctly:
```
Failed to load passes from 'nonexistant.so'. Request ignored.
Expected<T> must be checked before access or destruction.
Unchecked Expected<T> contained error:
Could not load library 'nonexistant.so': nonexistant.so: cannot open shared object file: No such file or directoryPLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.
```
Any tool using `lto::Config::PassPlugins` should suffer similarly.
Based on the message "Request ignored" and the continue statement, the
intention was apparently to continue on failure to load a plugin.
However, no one appears to rely on that behavior now given that it
crashes instead, and terminating is consistent with opt.
Commit: d058b51604eeb73bfc236bfe84e1ade90229950f
https://github.com/llvm/llvm-project/commit/d058b51604eeb73bfc236bfe84e1ade90229950f
Author: Momchil Velikov <momchil.velikov at arm.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
R llvm/test/CodeGen/AArch64/sitofp-to-tbl.ll
Log Message:
-----------
Revert "[AArch64] Lower extending sitofp using tbl (#92528)"
This reverts commit d1a4f0c9fb559eb4c2fb56112e56343bcd333edc.
There are reports about test failures with Eigen and JAX.
Commit: 22b36bfa3f18ef1cc858d3301c4eea00a280403a
https://github.com/llvm/llvm-project/commit/22b36bfa3f18ef1cc858d3301c4eea00a280403a
Author: Kazu Hirata <kazu at google.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/lib/ProfileData/MemProfReader.cpp
Log Message:
-----------
[Memprof] Fix a warning
This patch fixes:
llvm/lib/ProfileData/MemProfReader.cpp:685:1: error: non-void
function does not return a value in all con trol paths
[-Werror,-Wreturn-type]
While I am at it, this patch removes an else-after-return.
Commit: 6b1c51bc052ae974e89e623b3d143d010fd09222
https://github.com/llvm/llvm-project/commit/6b1c51bc052ae974e89e623b3d143d010fd09222
Author: Akash Banerjee <akash.banerjee at amd.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
M clang/lib/CodeGen/CGOpenMPRuntimeGPU.h
M clang/test/OpenMP/nvptx_target_parallel_reduction_codegen.cpp
M clang/test/OpenMP/nvptx_target_parallel_reduction_codegen_tbaa_PR46146.cpp
M clang/test/OpenMP/nvptx_teams_reduction_codegen.cpp
A clang/test/OpenMP/reduction_complex.c
M clang/test/OpenMP/reduction_implicit_map.cpp
M clang/test/OpenMP/target_teams_generic_loop_codegen.cpp
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
Log Message:
-----------
[OpenMP] Migrate GPU Reductions CodeGen from Clang to OMPIRBuilder (#80343)
This patch migrates the CGOpenMPRuntimeGPU::emitReduction and related functions to the OpenMPIRBUilder. In future patches MLIR OpenMP translation would be making use of these functions.
Co-authored-by: Jan Leyonberg <jan.leyonberg at amd.com>
Commit: a89a54190ced6f7ded24eb3b6e5115dbe69eada8
https://github.com/llvm/llvm-project/commit/a89a54190ced6f7ded24eb3b6e5115dbe69eada8
Author: Joel E. Denny <jdenny.ornl at gmail.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/test/Feature/load_plugin_error.ll
Log Message:
-----------
Fix test introduced by d29fdfbc4e3b
It breaks builds like:
https://lab.llvm.org/buildbot/#/builders/190/builds/744
Commit: 133492fe18260d4b5ce2d70ff9575fa9c911d090
https://github.com/llvm/llvm-project/commit/133492fe18260d4b5ce2d70ff9575fa9c911d090
Author: Schrodinger ZHU Yifan <yifanzhu at rochester.edu>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M libc/hdr/types/CMakeLists.txt
A libc/hdr/types/struct_sigaction.h
M libc/src/signal/linux/CMakeLists.txt
M libc/src/signal/linux/signal.cpp
M libc/src/signal/sigaction.h
M libc/test/src/signal/CMakeLists.txt
M libc/test/src/signal/sigaction_test.cpp
M libc/test/src/signal/sigaltstack_test.cpp
Log Message:
-----------
[libc] add proxy header for struct_sigaction (#96224)
Commit: 57d3d070502f54c63c5fca588cf74b78d607e272
https://github.com/llvm/llvm-project/commit/57d3d070502f54c63c5fca588cf74b78d607e272
Author: RoseZhang03 <rosezhang at google.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
A libc/newhdrgen/class_implementation/classes/enumeration.py
A libc/newhdrgen/class_implementation/classes/function.py
A libc/newhdrgen/class_implementation/classes/include.py
A libc/newhdrgen/class_implementation/classes/macro.py
A libc/newhdrgen/class_implementation/classes/object.py
A libc/newhdrgen/class_implementation/classes/type.py
Log Message:
-----------
[libc] added newhdrgen class implementation (#96710)
Added a class representation of a libc header file, allowing for easier
conversion from YAML to .h file output.
Classes include:
- Function (representing function headers)
- Include (representing various include statements found on a header
file)
- Macro (representing macro definitions)
- Enumeration (representing enum definitions)
- Type (representing include statements for NamedTypes)
- Object (representing ObjectSpec defintitions)
Commit: a54704de0d019760c80517b97bd1df636076a059
https://github.com/llvm/llvm-project/commit/a54704de0d019760c80517b97bd1df636076a059
Author: Heejin Ahn <aheejin at gmail.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M llvm/test/CodeGen/WebAssembly/target-features-attrs.ll
A llvm/test/CodeGen/WebAssembly/target-features-cpus.ll
Log Message:
-----------
[WebAssembly] Split and tidy up target features test (#96735)
This splits `target-features.ll` into two tests:
`target-features-attrs.ll` and `target-features-cpus.ll`.
Now `target-features-attrs.ll` contains tests with bitcode function
attributes and `-mattr=` options. The current `target-features.ll`
file's FileCheck lines are confusing, mainly because it is unclear how
`CHECK` and `ATTRS` lines are meant to be different. Turns out, before
https://github.com/llvm/llvm-project/commit/67ec8744d7e72b50a5db5038c9643584ce57cb0c,
`-mattr=` options used to override any existing bitcode function
attributes, but after the commit that's not the case anymore. So the
original test had a line that tested `i32.atomic.rmw.cmpxchg` was not
generated when `-mattr=+simd128` was given (because the existing
`+atomics` in the function attributes is overriden). That commit deleted
that line and changed some `ATTRS` lines into `CHECK`, which was
confusing. This PR simplifies that part and does not test the absence of
any instructions, and the effect of `-mattr=` option is only tested with
the target features section.
And `target-features-cpus.ll` only tests the sets of features enabled by
`-mcpu=` lines. It is better to have this as a separate file because
once you have bitcode function attributes they end up in the target
features section too, making the testing of only the `-mcpu=` options
difficult.
Commit: 915960fa793f061280c6cfcab2efeea281b06073
https://github.com/llvm/llvm-project/commit/915960fa793f061280c6cfcab2efeea281b06073
Author: shawbyoung <shawbyoung at gmail.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)
Changed paths:
M .github/CODEOWNERS
M bolt/docs/CommandLineArgumentReference.md
M clang-tools-extra/clang-tidy/misc/UseInternalLinkageCheck.cpp
M clang-tools-extra/clang-tidy/misc/UseInternalLinkageCheck.h
M clang-tools-extra/clang-tidy/tool/run-clang-tidy.py
M clang-tools-extra/docs/clang-tidy/checks/misc/use-internal-linkage.rst
A clang-tools-extra/test/clang-tidy/checkers/misc/use-internal-linkage-fix-mode-none.cpp
M clang-tools-extra/test/clang-tidy/checkers/misc/use-internal-linkage-func.cpp
M clang-tools-extra/test/clang-tidy/checkers/misc/use-internal-linkage-var.cpp
M clang/docs/LanguageExtensions.rst
M clang/include/clang/Basic/arm_sme.td
M clang/include/clang/Parse/Parser.h
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/lib/AST/Interp/ByteCodeExprGen.h
M clang/lib/AST/Interp/Interp.cpp
M clang/lib/AST/Interp/Pointer.h
M clang/lib/Analysis/FlowSensitive/Transfer.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
M clang/lib/CodeGen/CGOpenMPRuntimeGPU.h
M clang/lib/CodeGen/CodeGenAction.cpp
M clang/lib/Parse/ParseOpenMP.cpp
M clang/lib/Sema/ScopeInfo.cpp
M clang/test/AST/Interp/arrays.cpp
A clang/test/CodeGen/aarch64-sme2p1-intrinsics/acle_sme2p1_movaz.c
M clang/test/CodeGen/asan-frame-pointer.cpp
M clang/test/CodeGen/asan-globals.cpp
A clang/test/CodeGen/coverage-target-attr.c
M clang/test/CodeGen/sanitize-metadata-nosanitize.c
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx10.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx11.cl
M clang/test/OpenMP/nvptx_target_parallel_reduction_codegen.cpp
M clang/test/OpenMP/nvptx_target_parallel_reduction_codegen_tbaa_PR46146.cpp
M clang/test/OpenMP/nvptx_teams_reduction_codegen.cpp
A clang/test/OpenMP/reduction_complex.c
M clang/test/OpenMP/reduction_implicit_map.cpp
M clang/test/OpenMP/target_teams_generic_loop_codegen.cpp
M clang/test/SemaCXX/coroutine-vla.cpp
M clang/test/SemaCXX/cxx0x-initializer-stdinitializerlist.cpp
M clang/unittests/Analysis/FlowSensitive/TransferTest.cpp
M compiler-rt/include/profile/MIBEntryDef.inc
M compiler-rt/include/profile/MemProfData.inc
M compiler-rt/lib/memprof/memprof_allocator.cpp
M compiler-rt/lib/memprof/memprof_flags.inc
M compiler-rt/lib/memprof/memprof_mapping.h
M compiler-rt/lib/memprof/memprof_mibmap.cpp
M compiler-rt/lib/memprof/memprof_rawprofile.cpp
M compiler-rt/lib/memprof/memprof_rtl.cpp
M compiler-rt/lib/memprof/tests/rawprofile.cpp
M compiler-rt/lib/profile/InstrProfilingFile.c
M compiler-rt/test/profile/Linux/instrprof-vtable-value-prof.cpp
M flang/include/flang/Lower/BoxAnalyzer.h
M libc/config/linux/arm/entrypoints.txt
M libc/docs/gpu/support.rst
M libc/hdr/types/CMakeLists.txt
A libc/hdr/types/struct_sigaction.h
A libc/newhdrgen/class_implementation/classes/enumeration.py
A libc/newhdrgen/class_implementation/classes/function.py
A libc/newhdrgen/class_implementation/classes/include.py
A libc/newhdrgen/class_implementation/classes/macro.py
A libc/newhdrgen/class_implementation/classes/object.py
A libc/newhdrgen/class_implementation/classes/type.py
M libc/src/__support/OSUtil/linux/fcntl.cpp
M libc/src/__support/fixedvector.h
M libc/src/signal/linux/CMakeLists.txt
M libc/src/signal/linux/signal.cpp
M libc/src/signal/sigaction.h
M libc/src/stdlib/CMakeLists.txt
M libc/src/stdlib/rand.cpp
M libc/src/stdlib/rand_util.cpp
M libc/src/stdlib/rand_util.h
M libc/src/stdlib/srand.cpp
M libc/test/src/__support/fixedvector_test.cpp
M libc/test/src/fcntl/CMakeLists.txt
M libc/test/src/fcntl/fcntl_test.cpp
M libc/test/src/signal/CMakeLists.txt
M libc/test/src/signal/sigaction_test.cpp
M libc/test/src/signal/sigaltstack_test.cpp
M libc/test/src/stdlib/rand_test.cpp
M libcxx/docs/Status/Cxx20Issues.csv
M libcxx/include/__expected/expected.h
M libcxx/include/__memory/shared_ptr.h
M libcxx/include/__ranges/iota_view.h
M libcxx/include/__utility/pair.h
A libcxx/test/std/ranges/range.factories/range.iota.view/assert.ctor.value.bound.pass.cpp
M libcxx/test/std/utilities/expected/expected.expected/ctor/ctor.copy.pass.cpp
M libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.const/nullptr_t_deleter.pass.cpp
M libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.const/nullptr_t_deleter_allocator.pass.cpp
M libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.const/pointer.pass.cpp
M libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.const/pointer_deleter.pass.cpp
M libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.const/pointer_deleter_allocator.pass.cpp
A libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.const/types.h
M lld/ELF/InputSection.cpp
M lld/ELF/Relocations.cpp
M lld/test/ELF/as-needed-no-reloc.s
M lld/test/ELF/as-needed.s
M lld/test/ELF/auxiliary.s
M lld/test/ELF/dynamic-reloc.s
M lld/test/ELF/filter.s
M lld/test/ELF/gc-sections-shared.s
M lld/test/ELF/no-soname.s
M lld/test/ELF/partition-synthetic-sections.s
M lld/test/ELF/push-state.s
M lld/test/ELF/shared-ppc64.s
M lld/test/ELF/shared.s
M lld/test/ELF/soname.s
M lld/test/ELF/soname2.s
M lld/test/ELF/wrap-drop-shared-original.s
M lldb/bindings/interface/SBBreakpointDocstrings.i
M lldb/bindings/interface/SBDataExtensions.i
M lldb/docs/use/python.rst
M lldb/examples/python/armv7_cortex_m_target_defintion.py
M lldb/examples/python/crashlog.py
M lldb/examples/python/disasm-stress-test.py
M lldb/examples/summaries/cocoa/CFString.py
M lldb/examples/summaries/pysummary.py
M lldb/examples/synthetic/bitfield/example.py
M lldb/packages/Python/lldbsuite/test/dotest.py
M lldb/packages/Python/lldbsuite/test/lldbtest.py
M lldb/packages/Python/lldbsuite/test/lldbutil.py
M lldb/packages/Python/lldbsuite/test/tools/intelpt/intelpt_testcase.py
M lldb/source/Plugins/ObjectFile/Minidump/ObjectFileMinidump.cpp
M lldb/test/API/commands/command/script/welcome.py
M lldb/test/API/commands/expression/call-throws/TestCallThatThrows.py
M lldb/test/API/functionalities/breakpoint/address_breakpoints/TestBadAddressBreakpoints.py
M lldb/test/API/functionalities/disassemble/aarch64-adrp-add/TestAArch64AdrpAdd.py
M lldb/test/API/functionalities/gdb_remote_client/TestNoWatchpointSupportInfo.py
M lldb/test/API/functionalities/step_scripted/TestStepScripted.py
M lldb/test/API/functionalities/stop-on-sharedlibrary-load/TestStopOnSharedlibraryEvents.py
M lldb/test/API/lua_api/TestLuaAPI.py
M lldb/test/API/macosx/thread_suspend/TestInternalThreadSuspension.py
M lldb/test/API/python_api/event/TestEvents.py
M lldb/test/API/python_api/process/read-mem-cstring/TestReadMemCString.py
M lldb/test/API/python_api/type/TestTypeList.py
M lldb/test/API/python_api/was_interrupted/interruptible.py
M lldb/test/API/tools/lldb-server/TestAppleSimulatorOSType.py
M lldb/test/API/tools/lldb-server/TestLldbGdbServer.py
M lldb/test/Shell/lit.cfg.py
M llvm/CMakeLists.txt
M llvm/docs/AMDGPUUsage.rst
M llvm/docs/ReleaseNotes.rst
M llvm/include/llvm-c/Core.h
M llvm/include/llvm/ADT/APFloat.h
M llvm/include/llvm/ADT/SetOperations.h
M llvm/include/llvm/ADT/SmallPtrSet.h
M llvm/include/llvm/Analysis/VectorUtils.h
M llvm/include/llvm/CodeGen/SlotIndexes.h
M llvm/include/llvm/ExecutionEngine/Orc/Core.h
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/include/llvm/IR/ConstantRangeList.h
M llvm/include/llvm/IR/Function.h
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/include/llvm/IR/LLVMContext.h
M llvm/include/llvm/MC/DXContainerPSVInfo.h
M llvm/include/llvm/MC/MCContext.h
M llvm/include/llvm/MC/MCWinCOFFStreamer.h
M llvm/include/llvm/Object/ELFTypes.h
M llvm/include/llvm/ProfileData/MIBEntryDef.inc
M llvm/include/llvm/ProfileData/MemProf.h
M llvm/include/llvm/ProfileData/MemProfData.inc
M llvm/include/llvm/ProfileData/MemProfReader.h
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/SlotIndexes.cpp
M llvm/lib/CodeGen/WindowScheduler.cpp
M llvm/lib/ExecutionEngine/Orc/Core.cpp
M llvm/lib/ExecutionEngine/Orc/ObjectLinkingLayer.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/IR/ConstantRangeList.cpp
M llvm/lib/IR/Core.cpp
M llvm/lib/IR/Function.cpp
M llvm/lib/IR/LLVMContext.cpp
M llvm/lib/IR/LLVMContextImpl.h
M llvm/lib/LTO/LTOBackend.cpp
M llvm/lib/MC/MCContext.cpp
M llvm/lib/MC/MCDwarf.cpp
M llvm/lib/MC/MCObjectFileInfo.cpp
M llvm/lib/MC/MCWinCOFFStreamer.cpp
M llvm/lib/MC/WinCOFFObjectWriter.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/ProfileData/MemProfReader.cpp
M llvm/lib/Support/CMakeLists.txt
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/SMEInstrFormats.td
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h
M llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp
M llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp
M llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.h
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIProgramInfo.cpp
M llvm/lib/Target/AMDGPU/SIProgramInfo.h
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
M llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
M llvm/lib/Target/DirectX/DXContainerGlobals.cpp
M llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyExceptionInfo.cpp
M llvm/lib/Target/X86/X86FixupSetCC.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
M llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Analysis/ScalarEvolution/pr92560.ll
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/intrinsics.ll
M llvm/test/Bindings/llvm-c/echo.ll
R llvm/test/CodeGen/AArch64/sitofp-to-tbl.ll
A llvm/test/CodeGen/AArch64/sme2p1-intrinsics-movaz.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ptr.ll
M llvm/test/CodeGen/ARM/GlobalISel/fpenv.ll
M llvm/test/CodeGen/ARM/constant-islands-split-IT.mir
A llvm/test/CodeGen/DirectX/ContainerData/PipelineStateValidation.ll
M llvm/test/CodeGen/Hexagon/swp-ws-dead-def.mir
M llvm/test/CodeGen/Hexagon/swp-ws-exp-dbg.mir
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M llvm/test/CodeGen/Hexagon/swp-ws-fail-0.mir
M llvm/test/CodeGen/Hexagon/swp-ws-fail-1.mir
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M llvm/test/CodeGen/Hexagon/swp-ws-phi.mir
M llvm/test/CodeGen/Hexagon/swp-ws-sqrt.mir
M llvm/test/CodeGen/Hexagon/swp-ws-weak-dep.mir
M llvm/test/CodeGen/NVPTX/combine-mad.ll
M llvm/test/CodeGen/NVPTX/f16-instructions.ll
A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fcmp-f16-rv32.mir
A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fcmp-f16-rv64.mir
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A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-f16-rv32.mir
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A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-ext-trunc-f16.mir
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-f16-rv32.mir
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-f16-rv64.mir
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-f16-rv32.mir
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-f16-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-rv64.mir
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-f16-rv32.mir
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-f16-rv64.mir
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M llvm/test/CodeGen/RISCV/rv64zbb.ll
M llvm/test/CodeGen/SPIRV/const-nested-vecs.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_add/atomicrmw_faddfsub_float.ll
M llvm/test/CodeGen/SPIRV/pointers/global-zeroinitializer.ll
A llvm/test/CodeGen/SPIRV/pointers/irtrans-added-int-const-32-64.ll
M llvm/test/CodeGen/SPIRV/transcoding/OpGenericCastToPtr.ll
A llvm/test/CodeGen/WebAssembly/target-features-attrs.ll
A llvm/test/CodeGen/WebAssembly/target-features-cpus.ll
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M llvm/test/CodeGen/X86/apx/add.ll
M llvm/test/CodeGen/X86/apx/and.ll
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M llvm/test/CodeGen/X86/apx/ctest.ll
M llvm/test/CodeGen/X86/apx/dec.ll
M llvm/test/CodeGen/X86/apx/inc.ll
M llvm/test/CodeGen/X86/apx/neg.ll
M llvm/test/CodeGen/X86/apx/not.ll
M llvm/test/CodeGen/X86/apx/or.ll
M llvm/test/CodeGen/X86/apx/sar.ll
M llvm/test/CodeGen/X86/apx/sbb.ll
A llvm/test/CodeGen/X86/apx/setzucc.ll
M llvm/test/CodeGen/X86/apx/shl.ll
M llvm/test/CodeGen/X86/apx/shr.ll
M llvm/test/CodeGen/X86/apx/sub.ll
M llvm/test/CodeGen/X86/apx/xor.ll
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M llvm/test/CodeGen/X86/avgceils-scalar.ll
M llvm/test/CodeGen/X86/avgceilu-scalar.ll
M llvm/test/CodeGen/X86/avgfloors-scalar.ll
M llvm/test/CodeGen/X86/avgflooru-scalar.ll
M llvm/test/CodeGen/X86/popcnt.ll
M llvm/test/DebugInfo/X86/InlinedFnLocalVar.ll
M llvm/test/DebugInfo/X86/ref_addr_relocation.ll
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M llvm/test/Feature/load_plugin_error.ll
M llvm/test/Instrumentation/InstrProfiling/mcdc.ll
M llvm/test/MC/AMDGPU/hsa-sym-expr-failure.s
M llvm/test/MC/AMDGPU/hsa-sym-exprs-gfx10.s
M llvm/test/MC/AMDGPU/hsa-sym-exprs-gfx11.s
M llvm/test/MC/AMDGPU/hsa-sym-exprs-gfx12.s
M llvm/test/MC/AMDGPU/hsa-sym-exprs-gfx7.s
M llvm/test/MC/AMDGPU/hsa-sym-exprs-gfx8.s
M llvm/test/MC/AMDGPU/hsa-sym-exprs-gfx90a.s
M llvm/test/MC/AMDGPU/hsa-tg-split.s
M llvm/test/MC/AMDGPU/hsa-v4.s
M llvm/test/MC/AMDGPU/hsa-v5-uses-dynamic-stack.s
M llvm/test/MC/COFF/section-comdat-conflict.s
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A llvm/test/MC/COFF/section-sym-err.s
A llvm/test/TableGen/check-duplicate-tuple-regs.td
M llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
A llvm/test/Transforms/InstCombine/canonicalize-gep-mul.ll
M llvm/test/Transforms/InstCombine/getelementptr.ll
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-gather-scatter.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-phi.ll
M llvm/test/Transforms/LoopVectorize/AArch64/uniform-args-call-variants.ll
A llvm/test/Transforms/LoopVectorize/RISCV/vf-will-not-generate-any-vector-insts.ll
M llvm/test/Transforms/LoopVectorize/SystemZ/addressing.ll
A llvm/test/Transforms/LoopVectorize/WebAssembly/induction-branch-cost.ll
A llvm/test/Transforms/LoopVectorize/WebAssembly/lit.local.cfg
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/interleaving.ll
M llvm/test/Transforms/LoopVectorize/X86/optsize.ll
M llvm/test/Transforms/LoopVectorize/induction.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/scalable-inductions.ll
M llvm/test/Transforms/LoopVectorize/scalable-loop-unpredicated-body-scalar-tail.ll
M llvm/test/Transforms/LowerMatrixIntrinsics/multiply-fused-loops.ll
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M llvm/test/Transforms/PGOProfile/Inputs/memprof.memprofraw
M llvm/test/Transforms/PGOProfile/Inputs/memprof.nocolinfo.exe
M llvm/test/Transforms/PGOProfile/Inputs/memprof.nocolinfo.memprofraw
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M llvm/test/Transforms/PhaseOrdering/X86/pr67803.ll
A llvm/test/Transforms/SLPVectorizer/X86/insertelement-uses-vectorized-index.ll
M llvm/test/Verifier/AMDGPU/intrinsic-immarg.ll
M llvm/test/tools/llc/new-pm/pipeline.mir
M llvm/test/tools/llvm-ifs/write-stub.test
A llvm/test/tools/llvm-profdata/Inputs/basic-histogram.memprofexe
A llvm/test/tools/llvm-profdata/Inputs/basic-histogram.memprofraw
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M llvm/test/tools/llvm-profdata/Inputs/basic.memprofraw
A llvm/test/tools/llvm-profdata/Inputs/basic_v3.memprofexe
A llvm/test/tools/llvm-profdata/Inputs/basic_v3.memprofraw
M llvm/test/tools/llvm-profdata/Inputs/buildid.memprofexe
M llvm/test/tools/llvm-profdata/Inputs/buildid.memprofraw
M llvm/test/tools/llvm-profdata/Inputs/inline.memprofexe
M llvm/test/tools/llvm-profdata/Inputs/inline.memprofraw
M llvm/test/tools/llvm-profdata/Inputs/multi.memprofexe
M llvm/test/tools/llvm-profdata/Inputs/multi.memprofraw
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A llvm/test/tools/llvm-profdata/Inputs/padding-histogram.memprofraw
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M llvm/test/tools/llvm-profdata/Inputs/pic.memprofraw
M llvm/test/tools/llvm-profdata/Inputs/update_memprof_inputs.sh
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M llvm/test/tools/llvm-profdata/memprof-basic.test
A llvm/test/tools/llvm-profdata/memprof-basic_v3.test
M llvm/test/tools/llvm-profdata/memprof-inline.test
M llvm/test/tools/llvm-profdata/memprof-multi.test
A llvm/test/tools/llvm-profdata/memprof-padding-histogram.test
M llvm/test/tools/llvm-profdata/memprof-pic.test
M llvm/test/tools/llvm-profdata/vtable-value-prof.test
M llvm/test/tools/llvm-readobj/ELF/dynamic-malformed.test
M llvm/test/tools/llvm-readobj/ELF/dynamic-tags.test
M llvm/test/tools/llvm-readobj/ELF/loadname.test
M llvm/tools/llvm-c-test/echo.cpp
M llvm/tools/llvm-profdata/llvm-profdata.cpp
M llvm/tools/llvm-readobj/ELFDumper.cpp
M llvm/unittests/ADT/APFloatTest.cpp
M llvm/unittests/ADT/SetOperationsTest.cpp
M llvm/unittests/ADT/SmallPtrSetTest.cpp
M llvm/unittests/CodeGen/MLRegAllocDevelopmentFeatures.cpp
M llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
M llvm/unittests/IR/ConstantRangeListTest.cpp
M llvm/unittests/MC/AMDGPU/CMakeLists.txt
R llvm/unittests/MC/AMDGPU/SIProgramInfoMCExprs.cpp
M llvm/unittests/ProfileData/MemProfTest.cpp
M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
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M mlir/include/mlir/Dialect/ControlFlow/IR/ControlFlowOps.td
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M mlir/lib/Dialect/ControlFlow/IR/ControlFlowOps.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/lib/Transforms/Utils/DialectConversion.cpp
A mlir/test/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation/misc-other.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-bufferize.mlir
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